Cadence Announces Suite Approach that Bridges Hardware and Software to Reduce System Integration Time
May 5, 2011 -- Cadence Design Systems, Inc. today announced a new suite of products that promises to cut system integration time by up to 50% for next-generation designs. Bringing hardware and software development closer together, the suite features four connected platforms that enable hardware-software co-design from architectural-level development through to prototyping. No one company has offered the full suite of hardware-software development platforms until now, says Cadence.
Four essential platforms for system development
The Cadence System Development Suite features two new products — the Cadence Rapid Prototyping Platform and the Cadence Virtual System Platform — and connects them to the Cadence Palladium XP Verification Computing Platform and Cadence Incisive Verification Platform. The suite implements an integrated flow with a common environment that lets system engineers migrate quickly from one development phase to another.
"This integrated flow embodies the open, connected and scalable tenets of our approach to System Realization and provides a significant breakthrough in addressing the challenges of early software development and hardware/software convergence, leading to a dramatic reduction in development schedules," said Nimish Modi, Senior Vice President for the System and Software Realization Group at Cadence.
Smooth migration from emulation to FPGA-based prototyping
The Cadence Rapid Prototyping Platform includes off-the-shelf FPGA boards with capacities up to 30 million ASIC gates, supports standard ASIC flows and provides fast design mapping, multi-FPGA automatic partitioning and industry-leading FPGA place-and-route tools. Its unified environment with the Cadence Verification Computing Platform enables the fast and smooth migration of designs from emulation to FPGA-based prototyping. It delivers high-performance and affordable replicates for early software development and for running exhaustive regression tests while leveraging and sharing the fast bring-up times, superior debug capabilities and comprehensive SpeedBridge adapters' portfolio of the Cadence Verification Computing Platform.
Multiple views of hardware, software, memories and registers
The Cadence Virtual System Platform is a software development platform built on top of abstracted hardware models, approaching real-time speeds. It delivers an integrated and fully synchronized multi-core hardware software debug environment, with multiple views of hardware, software, memories and registers enabling system analysis and tight handshake between hardware and software teams.
Combined with the Cadence Incisive Verification Platform, it delivers mixed TLM/RTL unified simulation and common metric-driven verification methodology, reducing the risk of discrepancies between the abstracted hardware model and the eventual RTL. Finally, it accelerates the process of platform creation through automation by enabling customers to quickly build highly configurable transaction-level non-processors hardware models and utilize high-performance processor models delivered by ARM and other third parties.
"We have used Cadence emulation products for many years, including the Cadence Verification Computing Platform, for system validation on our most important projects, such as NVIDIA Tegra processors," said Narendra Konda, Director of Engineering at NVIDIA. "But with increased software content and multi-core designs, today's electronics systems have become substantially more complex and require a more robust set of technologies to meet time to market and ensure quality. Accordingly, we have deployed the broader Cadence System Development Suite, with elements such as the Cadence Rapid Prototyping Platform offering immediate incremental value."
"In order to streamline the system development process of ARM-based designs, we have collaborated with Cadence extensively over the last 10 years. The new Cadence approach of delivering a single environment for virtual prototyping, emulation and FPGA-based prototyping is clearly a need for future complex designs," said Joe Convey, Director of Design Enablement at ARM.
"The density of our Stratix IV FPGAs makes them an ideal device to be used in FPGA-based prototyping systems, and the new Cadence Rapid Prototyping Platform takes full advantage of the device's capabilities," said Vince Hu, Vice President of Product and Corporate Marketing at Altera. "Additionally, the productivity leadership of Altera's Quartus II software makes it a great match for the Cadence mission of reducing system integration time."
"Today's consumer electronics companies are struggling to cram more and more capabilities in their products, and then get these remarkably complex devices on shelves faster than the competition," said Chris Rommel, Senior Analyst with VDC Research. "The Cadence System Development Suite offers an intriguing approach that may help these companies shrink the overall development time significantly through tighter integration throughout the various phases of system development."
Reprinted from SOCcentral.com, your first stop for ASIC, FPGA, EDA, and IP news and design information.