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Facilitating At-Speed Test at RTL: Part 2Publication: EE Times EDA Designline April 20, 2011 -- Part 1 of this series discusses the problems with at-speed testing, and the various defect models and manufacturing test techniques. This part will tackle at-speed timing closure rules and at-speed coverage. It also looks into the at-speed coverage estimation and diagnosis of SpyGlass-DFT DSM. The SpyGlass-DFT DSM product provides timing closure analysis and RTL testability for deep subµm (DSM) defects associated with at-speed testing. It is touted to provide accurate RTL fault coverage estimation for transition delay testing, together with diagnostics for low fault coverage, early in the design flow.
By Dr. Ralph Marlett and Kiran Vittal. (Marlett is Product Director for Atrenta, Inc. and Vittal is Product Marketing Director, Atrenta, Inc.) | |
Reprinted from SOCcentral.com, your first stop for ASIC, FPGA, EDA, and IP news and design information. | |