Cadence Acquires Altos Design Automation
May 10, 2011 -- Cadence Design Systems, Inc. has acquired Altos Design Automation, Inc. Altos tools enable ultra-fast and accurate characterization of memory, standard cell libraries and other foundation IP, generating required models for SOC implementation. When combined with the Cadence end-to-end Silicon Realization portfolio, the offering gives designers greater visibility into the effects of noise, timing and power at every phase of the design cycle, including foundation IP design creation, extraction, Spice simulation, and implementation. The acquisition is another important step in delivering on the company's EDA360 vision.
"Foundation IP characterization is becoming mission critical at advanced nodes due to shrinking time-to-market windows, escalating low-power, high-speed design complexities, and variations in advanced processes," said Dr. Chi-Ping Hsu, Senior Vice President, Research and Development, Silicon Realization Group at Cadence. "By extending our Silicon Realization tool offering to include technically superior solutions that automate vital phases of the design process, we deliver the end-to-end approach that is required to ensure our customers' success."
Altos has over 30 customers, including 11 of the top 20 semiconductor companies. Terms of the acquisition were not disclosed.
Reprinted from SOCcentral.com, your first stop for ASIC, FPGA, EDA, and IP news and design information.