DOCEA Power Enhances "What-If" Power Analysis and Optimization
June 6, 2011 -- DOCEA Power will introduce and show an enhanced version of its flagship software product, Aceplorer 2.3, with a synthetic view for capturing the power architecture of complex designs at the 48th Design Automation Conference (DAC). This enables what-if analysis and optimization for hardware architecture and the target applications' use cases. Aceplorer models and optimizes electronic design power consumption, early in the design cycle, at the architectural level.
Aceplorer 2.3's new features are built on top of a parameterized power models library. They allow users to set up a complex system design with any number of intellectual property (IP) cores and blocks, voltage clusters or clock domain distributions at a fraction of the time needed with any other methodology.
DOCEA is demonstrating automatic scanning of power reduction techniques efficiencies on a design (dynamic voltage and frequency scaling (DVFS), clock gating, power gating and any combination thereof) and enabling architects to make better quality design decisions early in the process.
DOCEA Power's Aceplorer interoperability with Synopsys electronic system level (ESL) products is being demonstrated at Synopsys' Standards Booth #3328. This interoperability facilitates the import of power-related information for building complex and accurate dynamic scenarios, using performance analysis conducted on virtual platforms.
Reprinted from SOCcentral.com, your first stop for ASIC, FPGA, EDA, and IP news and design information.