Conexant Adopts Target's IP Designer Tool Suite to Build Next-Generation Foundation DSP IP
June 6, 2011 -- Target Compiler Technologies today announced that Conexant Systems, Inc. has adopted its IP Designer tool suite. Conexant is using IP Designer to design DSP cores in both its audio and imaging product lines. By using IP Designer, Conexant plans to deliver unprecedented efficiency in its programmable platforms, while retaining the benefits of programming in C.
Sverrir Olafsson, Vice President of Engineering at Conexant, comments, "We needed optimized DSP IP cores for our next-generation product lines, and we evaluated multiple avenues to address this need. IP Designer from Target Compiler Technologies allowed us to build our own highly-efficient DSP architectures within very well-contained development schedules and costs. The resulting optimized DSPs are well-tuned to the specific needs of our vertical markets and will provide greater efficiencies and better product differentiation for our customers."
is an EDA tool suite used by SOC designers to design, optimize and program DSPs and other such ASIPs (application-specific processor cores). The designer can easily describe ASIP architectures with performance and energy characteristics that are superior to commercially available processor IP (or may even approach the efficiency of hardwired data-paths). Using Target's processor modeling language (nML) and the IP Designer tool suite (which includes a highly optimizing C compiler, a cycle- or instruction-accurate instruction-set simulator, and a graphical/ interactive debugging/ profiling environment), designers can explore and fine-tune a processor architecture for performance and efficiency and then automatically generate low-power RTL and comprehensive verification suites.
Conexant's new DSPs will be programmable from C, enabling significant improvements in algorithm development and code portability and reuse. Olafsson noted that, "the efficiency of Target's C compiler allowed us to nearly eliminate assembly coding, which will help accelerate our time to market objectives. We were impressed by the level of support we received from Target throughout the entire development cycle."
Reprinted from SOCcentral.com, your first stop for ASIC, FPGA, EDA, and IP news and design information.