Vitesse Gigabit Ethernet IP Cores Enable Proliferation of Ethernet Applications
June 6, 2011 -- Vitesse Semiconductor Corp. today introduced a portfolio of Gigabit Ethernet intellectual property (IP) cores for simple and efficient integration of 10/ 100/ 1000BASE-T functionality into Ethernet IC solutions for consumer electronics, broadband access, network security, printer, smart grid, storage, and other applications.
With energy efficiency mandates such as Energy Star's upcoming Small Network Equipment specification and IEEE 802.3az 2010 Energy Efficient Ethernet (EEE), low power is critical for new Ethernet products. Vitesse's Gigabit Ethernet IP cores deliver industry-leading power dissipation below 390mW per port and feature Vitesse's EcoEthernet 2.0 power-saving technology. EcoEthernet includes fully compliant IEEE 802.3az EEE that can reduce power by 60% in idle mode. In addition, an ActiPHY-enabled mode reduces power by over 75% for ports with no link.
"Design constraints we faced mandated that we use a highly characterized Gigabit Ethernet PHY technology, and one with extremely low power dissipation," said Cheng-Te Chuang, Corporate Vice President of MediaTek, a vendor already in production with multiple ports of Vitesse's Gigabit Ethernet IP core. "Vitesse's solution embedded all of the necessary transceiver features for our applications to efficiently reach the market with integrated Ethernet connectivity."
Vitesse's Gigabit Ethernet IP core portfolio offers hard and soft macros for maximum flexibility, specifically including:
The cores are based on a power-efficient voltage-mode architecture with integrated line side resistors and low-EMI line drivers that provide extra margin for meeting residential emission standards. Their cable impairment active correction technology and robust DSP capabilities filter out cable noise and support remote cable diagnostics functionality. Carrier Ethernet (CE) versions of each core are also available. The CE versions offer multiple recovered clock outputs and fast link failover support ideal for use in G.8261 Synchronous Ethernet applications.
The hard macros, each fully routed designs that can improve time-to-market and reduce project risk, are provided with encrypted Verilog models; LVS netlist, GDS-II, and frame view LEF files; timing models; test benches for functional verification and production test-vector generation; Application Programming Interface source code; and documentation. The soft IP package (VSC9901-01) deliverables also include analog schematics, I/O cell netlists, RTL, and Verilog synthesis scripts.
The VSC9901-01, VSC9902-01 and VSC9903-01 are available immediately.
Reprinted from SOCcentral.com, your first stop for ASIC, FPGA, EDA, and IP news and design information.