 |
|
Power Optimization for Low-Power SOCs Targeting Mobile DevicesPublication: New Electronics Magazine June 29, 2011 -- Mobile devices are packing in more features than ever, pushing performance and bandwidth requirements to new levels. A plethora of new and evolving mobile devices, such as netbooks, tablets and smartphones, has introduced a convergence of computer, communication and consumer functionalities into a single device. The advanced baseband and application SOCs which power these mobile devices need to offer ever higher processing horsepower while still being powered by a battery. Reducing the power consumed by SOCs is essential in order to continue and add performance and features and continue the advancement of mobile devices. As a result, power optimization has become a top priority in SOC design. The total power consumed by a digital design consists of dynamic power and static (leakage) power. Dynamic power — the power consumed during device operation — is associated directly with processing load. Static power is the power consumed by the existing logic without any relation to the operation being performed. For modern SOCs, power optimization requires close attention to both dynamic power and leakage. | |
Reprinted from SOCcentral.com, your first stop for ASIC, FPGA, EDA, and IP news and design information. | |