IP Reuse and Design Management in the SOC and IC Design Process
Company: Gary Smith EDA
The areas of SOC/IC design processes that engineers stated needed the most advancement in the next two years are EDA verification tools, IP collaboration tools, EDA design tools, and embedded software tools. Based on a recent survey of 465 SOC designers and managers, the top two areas for investment were verification tools at 63%, and IP (intellectual property) collaboration and reuse tools at 50%. 42% selected EDA design tools and 26% selected embedded software tools.
Reprinted from SOCcentral.com, your first stop for ASIC, FPGA, EDA, and IP news and design information.