Static Formal Verification for System-Level Verification
Publication: Design & Reuse
October 7, 2011 -- Industrial data shows that verification takes about 70% to 80% of the total project development time. With increasing complexity of the SOC, system-level verification of the SOC is one of the key challenges to the verification teams. Improving time-to-market by reducing the project timelines, i.e., by reducing the effort on system-level verification without compromising on the quality of the deliverables is one of the challenges faced by the verification teams.
In this direction we have used static formal verification to complement the metrix-driven verification methodology in SOC verification. The scope of the article is to explain how to use formal verification for system-level verification and how it complements CDV-based methodology for system-level verification.
By Aniruddha Baljekar and Srinivas Puttur. (Baljekar and Puttur are with NXP Semiconductors Pvt. Ltd.)
Reprinted from SOCcentral.com, your first stop for ASIC, FPGA, EDA, and IP news and design information.