How to Test 3D Chips
Publication: Electronics Weekly
September 21, 2011 -- Semiconductor design is starting to see the adoption of 3D IC packages. These packages involve stacking multiple bare die vertically using connections that go directly though the silicon. Through-silicon vias (TSV) result in shorter and thinner connections that can be distributed across the die.
This reduces package size and power consumption while increasing performance due to the improved physical characteristics of the very small TSV connections compared to the much larger bond wires used in traditional packaging. But TSVs complicate the test process and 3D ICs require new approaches to solve this problem.
A challenge is how to test the TSV connections between the stacked memory and logic die. There is generally no external access to TSVs, making the use of automatic test equipment difficult at best.
Functional test approaches (for example, where an embedded processor is used to apply functional patterns to the memory bus) are possible but are slow, lack test coverage, and offer little to no diagnostics. Therefore, ensuring that 3D ICs can be economically produced calls for new test approaches.
One possible approach to the test and diagnostics challenges of memory on logic TSV connections builds upon built-in self-test (BIST) techniques that are used to test embedded memories within system-on-chip (SOC) devices.
By Stephen Pateras.
Reprinted from SOCcentral.com, your first stop for ASIC, FPGA, EDA, and IP news and design information.