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Minimizing Yield Fallout by Avoiding Over and Under At-Speed TestingPublication: EE Times Embedded September 30, 2011 -- In the nanometer technology used for automotive SOCs, most defects on silicon are due to timing issues. Thus, at-speed coverage requirements in automotive designs are stringent. To meet these requirements, engineers expend a lot of effort to get higher at-speed coverage. The principle challenge is to achieve silicon of the desired quality with high yield at the lowest possible cost. In this article we discuss the problems associated with over-testing and under-testing in at-speed testing, which can result in yield issues. We will provide a few suggestions that can help to overcome these problems.
By Rajiv Mittal and Amol Agarwal. (Mittal works at Advanced Micro Devices (AMD) as Senior Member of Technical Staff in ASIC/Layout Design Team in India; Agarwal is a Senior Design Engineer at Freescale Semiconductor, Inc.) | |
Reprinted from SOCcentral.com, your first stop for ASIC, FPGA, EDA, and IP news and design information. | |