Assertion-Based Verification Benefits FPGA designs
October 26, 2011 -- The change in FPGA capabilities has resulted in the emergence of advanced FPGA system-on-chip (SOC) solutions, which includes the integration of third-party IP, DSPs and multiple microprocessors, all connected through advanced, high-speed bus protocols. Accompanying these changes has been an increase in design and verification complexity, which traditional FPGA flows are generally not prepared to address.
This article considers an easy technique for addressing verification complexity by evolving an organisation's simulation process capabilities – specifically through the adoption of assertion-based verification (ABV).
By Harry Foster. (Foster is with Mentor Graphics Corp.)
Reprinted from SOCcentral.com, your first stop for ASIC, FPGA, EDA, and IP news and design information.