Challenges with Package-on-Package (PoP)
Company: DfR Solutions
The future of electronic package is 3D. From stacked die to Intel's recent introduction of the 3D transistor, the continued progression in Moore's Law is being accomplished by going "up." For the majority of design engineers, nowhere is this trend more concrete then the increasing utilization of components offered with a package-on-package (PoP) architecture.
Package-on-package is a configuration where two packaged integrated circuits are placed directly on top of each other (aka, stacked packages). The interconnects, or solder joints, are between the top package and the bottom package and the bottom and the PCB (note, some PoP configurations have more than two packages in the stack). The top package is traditionally thicker, containing multiple or stacked die, while the bottom package is thinner, with either smaller or thinner die. While various patents, and some commercial product, have focused on PoP with leaded devices, the overwhelming configuration is with ball grid array (BGA) technology.
As with all new technology introduced into the electronics marketplace, the prevalence of PoP has been greatly exaggerated. PoP recent ascendancy has been primarily been through a few high-volume manufacturers in the mobile and memory space. However, as PoP becomes a more common solution, it will become important for companies in low volume, high-rel applications to understand the technology's limitations in regards to manufacturability and reliability.
Reprinted from SOCcentral.com, your first stop for ASIC, FPGA, EDA, and IP news and design information.