Apache Design's Totem Software Adopted by Fujitsu Semiconductor for Power Noise And Reliability Analysis
December 12, 2011 -- ANSYS announced that Totem software, from its subsidiary Apache Design Solutions, Inc., has been deployed by Fujitsu Semiconductor, Ltd. to analyze and optimize all its custom IC designs. This includes analog, memory, high-speed I/O, PMICs (power-management ICs) and RF ICs that are used in a variety of consumer, mobile and communications electronic products. Totem, a complete power noise and reliability platform for analog/ mixed-signal chip designs, was selected by Fujitsu Semiconductor for its ability to handle large designs and analyze global noise coupling, which can impact chip performance and reliability. It was also chosen for its integration with existing analog-design-tool environments, a feature that offers improved productivity.
"Apache's Totem enables us to accurately model and simulate power/ ground, substrate and package/ PCB noise coupling at the full-chip level for advanced process technologies," said Masaru Ito, Director of the Technology Development Division, IP and Technology Development and Manufacturing Unit of Fujitsu Semiconductor. "By using Totem, we can explore the impact of noise coupling on the circuit's performance and determine if critical layout changes are needed early in the design process, allowing us to increase productivity and lower the risk of re-spin."
Totem is a full-chip, layout-based power noise and reliability platform for analog and mixed-signal designs. It addresses the challenges associated with global couplings of power/ ground noise, substrate noise, and package/ PCB capacitive and inductive noise for memory components (Flash and DRAM), high-speed I/Os (HDMI and DDR), and analog circuits such as power-management ICs. Totem-CSE considers the impact of full-chip SOC substrate noise and obtains an accurate substrate injection signature for all digital components. It accurately analyzes noise-coupling effects at every time-point using a single-kernel solver, and enables designers to account for all global noise impact on their designs. Totem-MMX is a transistor-level power-noise-analysis and verification solution for static and dynamic power integrity from early design stage to sign-off. It addresses the verification of IP designed using full-custom or semi-custom techniques for both analog and mixed-signal designs.
Reprinted from SOCcentral.com, your first stop for ASIC, FPGA, EDA, and IP news and design information.