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Synopsys Enables Silicon Success for GlobalFoundries' First Complex 20-nm DesignDecember 14, 2011 -- Synopsys, Inc. today announced that IC Compiler-Advanced Geometry (AG) drove silicon success for GlobalFoundries' first major 20-nm chip. Recently announced, IC Compiler-AG is the 20-nm edition of IC Compiler. The tape-out of this large design containing a dual-core processor represents a major milestone in the collaboration between Synopsys and GlobalFoundries to develop 20-nm rules and a comprehensive double-patterning technology (DPT)-aware implementation solution. The selection of IC Compiler for this critical design further strengthens IC Compiler's technological leadership in 20-nm design. Other components of Synopsys' Galaxy Implementation Platform were also used in the design, including . "We relied exclusively on IC Compiler-AG for the implementation of this complex 20-nanometer dual-core processor design," said Mojy Chian, Senior Vice President of Design Enablement at GlobalFoundries. "Furthermore, we extensively used IC Compiler Zroute technology for the necessary rule formulation to ensure manufacturability compliance. Our close collaboration with Synopsys resulted in robust implementation of DRC and double-patterning rules and enabled us to get to tape-out in time and with high manufacturing fidelity." At 20nm, as with prior process-node transitions, the challenges of managing power, performance, capacity and variability become progressively complicated. But, 20nm also introduces a clear, new challenge — double-patterning technology (DPT). This places an unprecedented burden on place-and-route tools to efficiently generate a layout which not only meets the traditional metrics mentioned above, but also can be decomposed into dual alternating patterns without undue impact on performance or device area. Typical solutions for DPT either force full complexity of DPT in the place-and-route tool, incurring potentially large run-time and die-size overhead, or rely on an implement-then-verify approach to verify DPT correctness with a physical-verification tool, risking multiple schedule-destroying iterations. Synopsys' IC Compiler-Advanced Geometry is built on Zroute and IC Validator In-Design physical verification technologies to deliver a noticeably superior DPT solution that minimizes die size and timing overhead while enabling the fastest path to design closure. Synopsys' approach to DPT keeps place-and-route performance efficient and avoids late-stage surprises, speeding the final tape-out. IC Compiler's DPT enhanced placement engine and Zroute routing technology work in tandem to efficiently generate a DPT-aware layout that can be verified and repaired for residual DPT violations using In-Design physical verification with IC Validator. GlobalFoundries is actively partnering with Synopsys to offer this flow concurrently with the commercial release of its 20-nm technology. | |
Reprinted from SOCcentral.com, your first stop for ASIC, FPGA, EDA, and IP news and design information. | |