Jitter and Timing Analysis In the Presence of Crosstalk
Publication: EE Times Test & Measurement Designline
December 14, 2011 -- Serial data standards continue to proliferate, providing dramatic improvements in PC and server-system performance. Testing these higher speed standards for evidence of jitter is critical for long-term stability and to achieving the objective of a good bit error ratio (BER) in the design. Effective analysis begins with selecting the right instruments and have a good understanding of instrument noise, rise time and factors such 3rd, 4th, 5th harmonic performance.
By Chris Loberg. (Loberg is a Senior Technical Marketing Manager at Tektronix, Inc. responsible for Oscilloscopes in the Americas Region.)
Reprinted from SOCcentral.com, your first stop for ASIC, FPGA, EDA, and IP news and design information.