Functional Coverage Analysis for IP Cores and an Approach to Scale Down Overall Simulation Time
Publication: Design & Reuse
January 3, 2012 -- This article presents functional coverage analysis automation and an approach to scale down overall simulation time. It is well known that functional verification of configurable IP cores is a real challenging task in any digital design development. Consequently, it is necessary to develop new methodologies to improve the quality of functional verification and also to decrease the time for regression convergence.
A metric that measures the functional coverage is specific to each design, and it depends on its functional requirements. Hence, we propose a methodology supported by any industry standard simulator that automates the coverage analysis at the functional level. We use functional metrics as parameters in our tool and apply theses metrics on an executable specification. Using our methodology, we are able to provide a quantitative evaluation of test suites developed to exercise the functionality defined in an executable specification. The application of these test suites on a RTL design improves quality and also increases the degree of confidence and reduces the overall simulation time. This approach has been followed in our functional verification of Configurable USB Host and Device IP controllers.
By Mohan Srikanth Sunkara and Raja Jagadeesan. (Sunkara and Jagadeesan are with Synopsys (India) Pvt. Ltd., Bangalore, India.)
Reprinted from SOCcentral.com, your first stop for ASIC, FPGA, EDA, and IP news and design information.