Synopsys and Arteris Enable Earlier Multicore SOC Architecture Optimization with Faster Turnaround Times
February 15, 2012 -- Synopsys, Inc. and Arteris, Inc. today announced a collaboration that enables models of Arteris' FlexNoC interconnect IP to be used with Synopsys' Platform Architect environment, offering system designers the ability to simulate realistic system-level performance of their end product architectures. SystemC transaction-level models (TLMs) generated by Arteris' FlexNoC configuration tool can now be easily united with Synopsys' architecture design models and traffic generators, enabling early analysis of end-application performance, and highly efficient optimization of multicore system architectures months before system software or register transistor language (RTL) designs are available.
With newly enhanced transactors and analysis monitor support for Arteris' FlexNoC interconnect models, Synopsys' Platform Architect environment with Multicore Optimization Technology (MCO) offers system architects three distinct advantages for early performance analysis and optimization of complex designs: 1) obtaining fully instrumented performance models before software and RTL availability, 2) clearly measuring and visualizing the dynamic behavior and performance bottlenecks of multicore designs, and 3) automating the design flow to enable developers to explore hundreds of architecture alternatives in days versus weeks or months with paper specifications and RTL methods. Now, architects using FlexNoC interconnect IP can take advantage of these features to more fully explore and optimize their multicore architectures and avoid the costly impact of over- or under-designing their SOCs.
Arteris and Synopsys' integration is available today for users of Arteris FlexNoC version 2.6 or later, and Synopsys' Platform Architect MCO tool version G-2011.06-SP2 or later.
Reprinted from SOCcentral.com, your first stop for ASIC, FPGA, EDA, and IP news and design information.