Synopsys and Arteris Develop IP Solution to Reduce Mobile Phone Memory Costs
February 29, 2012 -- Synopsys, Inc. and Arteris SA today announced their joint analog and digital IP solutions to implement the MIPI Alliance Low Latency Interface (LLI) 1.0 specification. The combined offerings deliver high performance with low power consumption in a compact silicon footprint while providing interoperability with the MIPI standard.
By providing a collaborative solution that adheres to the LLI specification, Arteris and Synopsys give system-on-chip (SOC) designers access to pre-tested and pre-optimized analog and digital MIPI-based IP that can reduce design cost and accelerate time to market.
The MIPI Alliance LLI specification enables high-bandwidth, low-latency inter-chip communication between two chips using a minimal number of SOC pins. The LLI specification utilizes the MIPI M-PHY physical layer, which also supports five other protocols including USB SSIC, JEDEC UFS, MIPI CSI-3, DSI-2 and DigRF v4. The round-trip latency of the LLI inter-chip connection is fast enough for a mobile phone modem to share an application processor's memory while maintaining enough read throughput and low latency for cache refills. This enables phone manufacturers to remove the modem's dedicated RAM chip from the phone's bill-of-materials, MIPI Alliance estimates saving approximately $2 in cost per phone as well as significant printed circuit board (PCB) space that can be used for additional features or to create smaller or thinner devices.
The joint solution consists of Arteris' Flex LLI MIPI LLI digital controller IP and Synopsys' DesignWare MIPI M-PHY IP. A team of Arteris and Synopsys engineers, formed to facilitate verification and testing of the joint solution, validated its functionality and interoperability.
Arteris and Synopsys' joint MIPI LLI IP solution is available today for select early access customers to start their design. System hardware implementing the joint solution will also be available in the second half of 2012.
Reprinted from SOCcentral.com, your first stop for ASIC, FPGA, EDA, and IP news and design information.