Top-level Custom Signal Planning and Routing
Publication: EE Times EDA Designline
February 20, 2012 -- Market requirements are driving custom and analog/ mixed-signal (AMS) IC providers to develop ICs with ever-increasing complexity and performance. Current custom ICs are outgrowing the capabilities of conventional custom design techniques that involve traditional point tools, schematics, Spice-level netlists, manual layout tools, manual routing, plus some scripting to improve design throughput. Design limitations are especially pronounced in the areas of hierarchical floor planning, signal and bus planning and routing, design change incorporation, and project coordination.
What about using advanced digital IC design tools to help automate the custom design effort? Advanced digital IC floor planning, signal planning, and routing tools rely on the highly standardized digital design ecosystem, and remain largely ineffective when faced with custom IC design challenges that include irregular libraries, limited model availability, limited metal stacks, unusual physical topologies, extremely deep design hierarchies, lack of routing grids, lack of placement grids etc. Some of the approaches that have been used in digital design automation can be adapted to support custom IC signal planning and routing. However, don't expect solutions from large digital IC design tool providers, the custom market space remains too small and too fragmented to justify the effort. Future solutions will largely come from smaller specialized custom design automation suppliers.
This article gives an overview of a proven methodology that relies on hierarchical custom design tools that can be used to resolve hierarchical signal planning and routing issues. The following topics will be covered: floor planning, power planning, bus long net and datapath planning, signal planning and routing, route fixing and optimization, and guided design flows.
By Bob Eisenstadt. (Eisenstadt is Senior Technologist, Pulsic, Ltd.)
Reprinted from SOCcentral.com, your first stop for ASIC, FPGA, EDA, and IP news and design information.