STATS ChipPAC's Scalable 3D eWLB Solutions Deliver Performance, Height and Cost Advantages


March 7, 2012 -- STATS ChipPAC, Ltd. has announced its next-generation three-dimensional (3D) embedded Wafer Level Ball Grid Array (eWLB) Package-on-Package (PoP) solutions. This new 3D technology provides an ultra-thin package profile height below 1.0mm, a 30% height reduction over the industry-standard 1.4-mm total stacked-package height.

PoP has been a successful 3D packaging approach by virtue of the flexibility it offers in combining individual memory and logic packages vertically into a single solution in the industry standard 1.4-mm total stacked-package height. While current PoP technologies are effective in integrating multiple functions in a small form factor, reaching the next level of packaging bandwidth and performance in more advanced mobile devices drive advancements in the stacked package profile height below 1.0mm as well as tighter substrate line/ space capability.

STATS ChipPAC's eWLB PoP technology offers significant performance, cost and height advantages over traditional substrate-based PoP technology. By utilizing eWLB's fan-out wafer-level packaging approach, STATS ChipPAC has been able to reduce the bottom PoP package height to less than 0.5mm. eWLB PoP is available in either a single or double-sided configuration and provides a flexible integration platform for stacking a wide range of memory packages on top with a final stacked package height below 1.0mm.

"eWLB has proven to be a scalable advanced technology that opens up a number of opportunities for our customers in terms of product design," said Hal Lasky, Executive Vice President and Chief Sales Officer, STATS ChipPAC. "In addition to mobile applications, there has been a growing interest from customers in computing applications where fanning out the device interconnection using eWLB technology can reduce substrate complexity and costs. eWLB is also well-suited for the microcontroller market where reducing cost and form factor are a priority,"


Reprinted from SOCcentral.com, your first stop for ASIC, FPGA, EDA, and IP news and design information.
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