Altera and TSMC Jointly Develop Heterogeneous 3D IC Test Vehicle Using CoWoS Process
March 22, 2012 -- Altera Corp. and TSMC (Taiwan Semiconductor Manufacturing Company) today announced the joint development of the first heterogeneous 3D-IC-test vehicle using TSMC's Chip-on-Wafer-on-Substrate (CoWoS) integration process. TSMC's integrated CoWoS process provides semiconductor companies developing 3D ICs an end-to-end solution that includes the front-end manufacturing process as well as back-end assembly and test solutions.
Altera is the first semiconductor company to develop and complete characterization of a heterogeneous test vehicle using TSMC's CoWoS process. This and additional test vehicles enable Altera to quickly test the capabilities and reliability of 3D ICs to ensure they meet yield and performance targets. TSMC's CoWoS process combined with Altera's technology leadership in silicon and intellectual property (IP) lays the foundation for rapid and cost-effective 3D IC product development and deployment in the future.
Altera's vision for heterogeneous 3D ICs includes developing device derivatives that allow customers to mix and match silicon IP based on their application requirements. Altera will leverage its position in FPGA technology and integrate various technologies with an FPGA, including CPUs, ASICs, ASSPs, memory and optics. Altera's 3D ICs enable developers to differentiate their applications by leveraging the flexibility of the FPGA, while maximizing system performance, minimizing system power and reducing form factor and system cost.
CoWoS is an integrated process technology that attaches device silicon chips to a wafer through a chip-on-wafer (CoW) bonding process. The CoW chip is attached to the substrate (CoW-On-Substrate) to form the final component. By attaching the device silicon to the original thick wafer silicon before it finishes the fabrication process, manufacturing-induced warping is avoided. TSMC plans to offer CoWoS as a turnkey manufacturing service.
Reprinted from SOCcentral.com, your first stop for ASIC, FPGA, EDA, and IP news and design information.