IDT RapidIO Gen2 Interface Selected for High-speed Interconnect on TI's TMS320C665x Multicore Processors
March 26, 2012 -- Integrated Device Technology, Inc. (IDT) today announced that IDT's RapidIO Gen 2 interface intellectual property (IP) has been selected by Texas Instruments, Inc. (TI) for its new TMS320C665x multicore digital signal processors (DSPs).
IDT's RapidIO Gen2 interface operates at an aggregate bandwidth of up to 20Gbps using four serial lanes, each at up to 6.25Gbaud. The IDT IP is preferred by DSP, microprocessor, and ASIC vendors for multiprocessor communication due to its inherent interoperability with IDT's portfolio of RapidIO Gen2 switches. By using IDT's RapidIO Gen 2 interface with IDT switches, OEMs are able to deliver embedded systems with twice the interconnect throughput and an order of magnitude lower end-to-end packet termination latency compared to 10GbE solutions, along with very low 100ns cut-through latencies through IDT switches.
"IDT's RapidIO Gen2 interface technology offers tremendous scalability benefits to our customers," said Ramesh Kumar, Business Manager, Multicore Processors, Texas Instruments. "We are now delivering the most mature RapidIO interfaces for interconnectivity across our DSP portfolio and have selected RapidIO because of its inherent performance attributes for DSP aggregation, such as 10 GbE."
RapidIO enables OEMs to design systems with clusters of DSPs that communicate in a scalable peer-to-peer fashion with simplified memory maps and reliable packet transmission. "RapidIO is the ideal choice for clustering multiple processors that require peer-to-peer communication, reliability, scalability, and high performance in a single interconnect," said Tom Sparkman, Vice President and General Manager of the Communications Division at IDT.
Reprinted from SOCcentral.com, your first stop for ASIC, FPGA, EDA, and IP news and design information.