How Designers Can Increase Parametric Yield
Publication: eeDesign (EE Times EDA News)
November 21, 2003 -- One of the major challenges facing semiconductor companies today is how to increase yield. Since yield is directly related to profitability, by predicting and improving yield before tapeout, an IC designer can have a direct dollar impact on the success of his design.
The ability to predict and improve yield becomes even more vital as processes move to geometries under 100 nanometers. In fact, there are dismal predictions that yields for ICs with geometries below 100 nanometers may not exceed 50 or 60 percent. To account for process variations, an IC designer not only has to design for good electrical performance, but also design for high manufacturing yield. EDA companies need to develop tools and methodologies that designers can easily incorporate into their flow to meet this challenge.
By Tina Najibi. (Najibi is an architect on the Custom IC team at Cadence Design Systems, Inc.)
Reprinted from SOCcentral.com, your first stop for ASIC, FPGA, EDA, and IP news and design information.