Optimizing Performance, Power, and Area in SOC Designs Using MIPS Multi-Threaded Processors
Publication: EE Times EDA Designline
April 4, 2012 -- Hardware-based multi-threading technology has for some time been known in the industry as a feasible technique for improving system performance, but not too many people are aware of just how much traction the technology has gained since its early implementations in the 1960s.
This article provides a brief history of hardware based multi-threading and some examples of its commercial adoption so far. It then gives an overview of the fundamental value of multi-threading in hardware, and describes MIPS Technologies' multi-threading architecture and product offerings. The article also provides several multi-threaded application examples, including those in the areas of driver assistance systems and home gateways, to demonstrate the broad applicability of multi-threading in real-world applications.
By Delfin Rodillas. (Rodillas is a Marketing Director for the Networks Markets at MIPS Technologies, Inc.)
Reprinted from SOCcentral.com, your first stop for ASIC, FPGA, EDA, and IP news and design information.