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Design Sallen-Key Low-Pass Filters Above 1; Achieve Lower Output NoisePublication: EDN Magazine April 9, 2012 -- It is common to see higher-order, multistage, Sallen-Key filters designed with each stage at a gain of 1. This has component-sensitivity advantages, but always produces significant noise-gain peaking within the filter stages themselves for the higher-Q stages. While it often might be the case that the SNR is already defined by the input signal before it hits an active filter stage, if the same filter response can be achieved, and produce considerably lower noise contribution to the signal path, why not? A detailed analysis of the noise gain response within the Sallen-Key stage exposes this noise gain-peaking issue and shows it only takes a slight increase from a gain of 1 to get a significant drop in noise peaking, thus reducing the output integrated noise due to the filter stage itself. This lengthy and detailed article, complete with numerous figures, equations, and analyses, will benefit anyone who is looking to optimize noise performance. It is presented as a single document in Word format.
By Michael Steffes. (Steffes is Senior Applications Manager, Intersil Corp.) | |
Reprinted from SOCcentral.com, your first stop for ASIC, FPGA, EDA, and IP news and design information. | |