Fraunhofer and Intopix Present DCP Creation with Real-Time JPEG 2000 Coding
April 16, 2012 -- The Fraunhofer Institute for Integrated Circuits IIS and IntoPIX s.a. have cooperated to accelerate the creation process and mastering of digital cinema packages (DCP). The easyDCP software package developed by Fraunhofer IIS now supports the Pristine hardware-acceleration board from Intopix to allow for faster encoding of JPEG 2000 files, both visually or mathematically loss-less, for resolutions from HD up to 4K.
The most time-consuming part of DCP processing is the encoding and decoding of image files to and from standard compliant JPEG 2000 files. The easyDCP creator typically uses the computational power of CPUs in multiple threads for the creation of digital cinema packages. Also the Curator software of IIS, which is especially designed for digital archiving where mathematically loss-less compression is required, works in the same way for the creation of digital archive packages.
"Depending on the requirements and delivery constraints, there is a demand for higher encoding speeds in professional environments. This demand for creating DCPs and archival packages in real-time or even faster can be met by using hardware acceleration," explains Heiko Sparenberg, head of the Digital Cinema group at Fraunhofer IIS. "The pool of expertise of IIS and IntoPIX for JPEG 2000 compression led to a solution which enables the user to choose between an easyDCP software-only solution or to pitch on a hardware acceleration with easyDCP and the Pristine board. DCPs can then be created with more than 24 frames per second."
"Together with Fraunhofer, we have done a seamless integration of the Pristine board into the easyDCP Creator workflow. The standard PCI-Express (8 Lanes) interface supports fast communication between the easyDCP software and the hardware-acceleration board, where the encoding is done," says Jean-Baptiste Lorent, Product Manager from Intopix. "Workflows for digital cinema production or lossless archiving will profit from this combination."
Reprinted from SOCcentral.com, your first stop for ASIC, FPGA, EDA, and IP news and design information.