Samsung Electronics Tapes Out Gigahertz+ ARM Cortex-A15 Processor with Synopsys IC Compiler
April 30, 2012 -- Synopsys, Inc. today announced the collaboration between Synopsys and Samsung Electronics on the implementation of an ARM Cortex-A15 MPCore processor. The processor core was implemented by Samsung Austin Research Center (SARC) using Synopsys place-and-route technology, a cornerstone of the Synopsys Galaxy Implementation Platform. Running at operating speeds in excess of a 1GHz on Samsung's 32-nm low-power process, the hardened core has already been deployed in the industry's first Cortex-A15 processor-based SOC for mobile computing devices. The high speed was enabled through a combination of optimization techniques and differentiated high-performance technologies.
"Globally, this was the first production tape-out of a Cortex-A15 processor and we relied exclusively on IC Compiler and the Galaxy tool suite to predictably achieve our performance and power targets," said Keith Hawkins, Vice President, SARC.
Samsung fabricated the three–million-instance, dual-core Cortex-A15 processor on a 32LP high-K metal gate (HKMG) process. Synopsys collaborated closely with SARC on an implementation methodology based on key high-performance technologies and optimization techniques in the Galaxy Implementation Platform to meet Samsung's stringent mass-production criteria for an on-time tape-out. The processor core relied on Physical Datapath in Design Compiler Topographical and IC Compiler for the structured placement of registers to meet power and area objectives. Layout-based debug with Design Compiler Topographical allowed quick analysis of library, netlist and placement issues to close timing. Clock mesh in IC Compiler and PrimeTime provided the low skew and increased on-chip-variation (OCV) tolerance necessary for the high-performance core.
Reprinted from SOCcentral.com, your first stop for ASIC, FPGA, EDA, and IP news and design information.