Atrenta Ships 4.7 Release of SpyGlass Platform
May 1, 2012 -- Atrenta Inc. announced today the availability of release 4.7 of its SpyGlass RTL analysis and optimization platform. This latest release of SpyGlass delivers automated RTL power reduction that is, on average, 2X more effective across a broad range of designs when compared to previous releases. Run-time and memory usage have also been enhanced in 4.7, with users reporting running 280-million-gate designs flat through SpyGlass in four hours.
Many of the analysis features of SpyGlass have also been improved. UPF 2.0 support has been extended in SpyGlass Power Verify. A power-intent-aware CDC analysis has been introduced that enables early verification of CDC issues around isolation logic at RTL. Glitch-detection reporting has been enhanced and SpyGlass DFT DSM now provides at-speed testability analysis that is more comprehensive. SpyGlass Constraints analysis now enables designers to consolidate SDCs associated with different modes into a single SDC through an SDC mode-merge capability.
New features in SpyGlass 4.7 include an improved user interface for SpyGlass Physical that provides designers the capability to quickly analyze and pinpoint logical congestion issues within their RTL. Also included in this release is a unique design-complexity analysis addition to SpyGlass Advanced Lint based on cyclomatic metrics. The Atrenta Console graphical user interface also provides several usability enhancements for netlist and schematic viewing.
Reprinted from SOCcentral.com, your first stop for ASIC, FPGA, EDA, and IP news and design information.