Key Methods for Controlling EMC
Publication: EE Times Test & Measurement Designline
May 7, 2012 -- Increasing clock speeds, coupled with high-frequency bus and interface data rates, make PC board design significantly more challenging. Engineers have to look beyond the design of the actual logic on the board to other factors that can affect circuits, such as board size, environmental noise, power consumption and electromagnetic compatibility (EMC). Hardware engineers should address EMC issues during the PC board design phase to ensure a system free of EMC faults.
By Ashish Kumar and Pushek Madaan. (Kumar is senior product engineer at Cypress Semiconductor India Pvt., Ltd. and Madaan is senior application engineer at Cypress Semiconductor India.)
Reprinted from SOCcentral.com, your first stop for ASIC, FPGA, EDA, and IP news and design information.