A Digital Design Flow for Differential ECL High-Speed Applications
Publication: Design & Reuse
May 3, 2012 -- This article presents a digital design flow in order to design high-performance differential Emitter Coupled Logic (ECL) circuits efficiently. The proposed flow is similar to the ordinary digital CMOS design flow. It uses standard design tools for and layout generation.The differential logic synthesis is separated in two phases. Starting from a synthesized, single-ended HDL design description, a fully differential ECL netlist is generated using a Verilog netlist converter before the layout phase. This results in a short development time and fast verification possibilities. Furthermore, the layout generation can be done in one shot together with digital CMOS components.
By Oliver Schrape, Milos Krstic, Gunnar Philipp, and Frank Winkler. (Schrape and Krstic are with, IHP, Frankfurt (Oder), Germany; Philipp and Winkler are with Humboldt University, Berlin, Germany.)
Reprinted from SOCcentral.com, your first stop for ASIC, FPGA, EDA, and IP news and design information.