 |
|
ADC Performance: What's Jitter Got to Do with It?Publication: Electronic Design Magazine April 25, 2012 -- Meeting the demanding performance requirements of today's system-on-chip (SOC) applications, whether in high-data-rate telecom systems or high-quality audio and video equipment, requires extensive signal processing. Data converters are an essential element of the signal processing chain. However, the performance of systems incorporating data converters depends, to a large extent, on the sampling clock's quality. Uncertainty of the time instant when the analog-to-digital converter (ADC) samples the signal, defined as clock jitter, increases conversion noise, which reduces the overall system performance. The effect of jitter on ADCs' sampling error can best be handled by focusing on the frequency domain of the corresponding phase noise representation of jitter.
By Carlos Azeredo-Leme. (Azeredo-Leme is a senior staff engineer for the DesignWare analog IP group at Synopsis, Inc.) | |
Reprinted from SOCcentral.com, your first stop for ASIC, FPGA, EDA, and IP news and design information. | |