STMicroelectronics Tapes Out 20-nm Test Chip Using Cadence Tools
May 31, 2012 -- Cadence Design Systems, Inc. today announced that it has contributed to STMicroelectronics having taped out a 20-nm test chip, incorporating custom analog and digital methodologies to enable mixed-signal SOC design at this advanced process node. Engineers from the two companies collaborated closely to develop technologies and deploy methodologies using the Cadence Encounter and Virtuoso platforms to enable design, implementation and sign-off, in addition to development of foundational IP and a SKILL-based process design kit (PDK) for the 20-nm process.
As part of this collaboration, STMicroelectronics has deployed the full Cadence 20-nm flow, physical IP libraries and the related PDK.
ST performed automated layout generation using Cadence Virtuoso Layout Suite into STMicroelectronics' custom-IP-design development, including foundation IP, PLL and video DAC. To help ensure accurate results, designers used a 20-nm PDK that enables advanced capability such as Modgens, constraints and space-based routing. The Encounter Digital Implementation (EDI) System provided 20-nm physical implementation capabilities for the tape-out, handling 20-nm process requirements during placement and optimization as well as routing.
Reprinted from SOCcentral.com, your first stop for ASIC, FPGA, EDA, and IP news and design information.