 |
|
A Look Inside Behavioral SynthesisPublication: eeDesign (EE Times EDA News) April 08, 2004 -- Behavioral synthesis is an automated design process that interprets an algorithmic description of a desired behavior and creates hardware that implements that behavior. It is used as part of a behavioral design flow that promises to raise the level of abstraction of the design process. This can be shown to increase designer productivity and reduce the opportunity for error. Starting with an algorithmic description in a high-level language, behavioral synthesis tools automatically create the cycle-by-cycle detail needed for hardware implementation. Most behavioral synthesis approaches leverage the existing logic synthesis toolset by creating a register transfer level (RTL) implementation from the algorithmic description. This RTL is used directly in a conventional logic synthesis flow to create a gate-level implementation. These behavioral synthesis tools transform untimed or partially timed functional code into fully timed RTL implementations. A behavioral design flow using behavioral synthesis lets the designer focus on the module functionality and the interconnect protocol. The design of the micro-architecture and the cycle-by-cycle timing are handled by the behavioral synthesis toolset. A review of the literature indicates that designing at a higher level of abstraction using behavioral synthesis reduces the amount of code that must be developed by as much as two thirds. These users report overall reduction of design effort of 50% or more. By Michael Meredith. Meredith is Vice President of Technical Marketing at Forte Design Systems | |
Reprinted from SOCcentral.com, your first stop for ASIC, FPGA, EDA, and IP news and design information. | |