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At-Speed Testing Made EasyPublication: eeDesign (EE Times EDA News) June 03, 2004 -- Today's chip designs are getting smaller and bigger. Feature sizes are moving into nanometer geometries, and gate counts are pushing towards the 100M gate mark. Semiconductor companies creating these nanometer designs are struggling with many issues that result from this shrinking yet increasingly complex design environment. One issue growing in importance is creating high quality, cost-effective tests for these devices. Companies on the leading-edge of nanometer design discovered the hard way that new types of defects are occurring in these complex nanometer designs. A much higher proportion of the defects are timing related than in previous designs that used older chip manufacturing processes and materials . The defect spectrum now includes more problems such as high impedance shorts, in-line resistance, and crosstalk between signals, which are not always detected with the traditional static-based tests, known as stuck-at tests. By Bruce Swanson and Michelle Lange. (Swanson is a technical marketing engineer and Lange is a marketing manager in the Design-for-Test group at Mentor Graphics Corp.) | |
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