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Using Formal Verification to Create Robust IPPublication: eeDesign (EE Times EDA News) July 30, 2004 -- Given the criticality of IP in today's designs, it is vital that an IP provider thoroughly verify each design before it is used in SoC projects. This is equally true for designers providing blocks for reuse within their company, often via an internal design repository, and commercial providers. A designer's job may hinge upon how well his or her blocks can be leveraged by other projects in the company. A commercial IP provider's very existence relies on positive customer experience and a good reputation. SoC designers evaluating IP also know the importance of verification, but it can be very hard to assess verification quality for a block designed by someone else. Today, this assessment is accomplished by inquiring about past user experience and evaluating the verification methods used by the IP provider. As this article will discuss, current methods leave some gaps in IP verification and therefore some shortfalls in the metrics used to gauge verification thoroughness. By Jay Littlefield. (Littlefield is Director of Applications Engineering at Real Intent, Inc.) | |
Reprinted from SOCcentral.com, your first stop for ASIC, FPGA, EDA, and IP news and design information. | |