Symmetric Design Technique Facilitates Power Analysis
Publication: eeDesign (EE Times EDA News)
September 03, 2004 -- Increased operating frequency, power density and lower supply voltages place increasing demands on the power distribution networks of systems containing large-scale integrated circuits. Large, rapid changes in supply current are caused by simultaneous gate switching, rapid pre-charging, and gating techniques for power saving.
These changes give rise to powerful transients in on-chip, package and board level power grids. Careful power planning is necessary to reduce these transients, which otherwise can cause timing errors, increased stress in thin gate oxides, and circuit failure.
Power supply-related noise coupling is very hard to analyze using traditional circuit simulation techniques such as Spice. The size of the netlist required to simulate a multi-chip system, and the analysis of the complex multiple couplings between power supply and signal nets, have prevented proper simulation-based power grid design.
This paper describes a design technique and simulation methodology which allows the simultaneous analysis of all chip, package and board level components. By separating the power net into a global net and a local net, the problem can simplified to the point where simulation run times can be reduced by many orders of magnitude. In the global net, most of the energy is stored in the magnetic field and dissipated as heat; in the local net, almost all of the energy is stored in the electric field. These techniques also have the advantage of reducing unwanted radiation and coupling between power and signal nets.
By Donald Bennett. (Bennett is a device physicist and IC design engineer who now develops and markets the system level power planning and analysis tool Picosim at Quantum Design Automation.)
Reprinted from SOCcentral.com, your first stop for ASIC, FPGA, EDA, and IP news and design information.