| Aldec Launches Spec-TRACER Requirements Lifecycle Management for Safety-critical FPGA and ASIC Designs |
May 20, 2013 -- Aldec, Inc., a pioneer in mixed-language simulation and advanced design tools for FPGA and ASIC devices, today announced the launch of Spec-TRACER™, a new requirements lifecycle management solution for use in safety-critica ... read more |
| Category: News: News Archive 2013: |
| Altera Stratix V GX FPGAs Achieve PCIe Gen3 Compliance and Listing on PCI-SIG Integrators List |
May 21, 2013 -- Altera Corp. today announced that its 28-nm Stratix V GX FPGAs have achieved inclusion on the latest PCI-SIG Integrators List for the PCI Express (PCIe) 3.0 specification (Gen3). Stratix V GX FPGAs successfully p ... read more |
| Category: News: News Archive 2013: |
| Ausdia Receives Patent for System and Method for Automatically Managing Clock Relationships in IC Designs |
May 20, 2013 -- Ausdia, Inc. has been issued patent number US 8,438,517 B2 by the United States Patent and Trademark Office. The patent discloses automated techniques for identifying and managing the relationship between clock domains in ... read more |
| Category: News: News Archive 2013: |
| BittWare Joins Altera Preferred Board Partner Program for OpenCL |
May 20, 2013 -- BittWare, Inc., a maker of Altera-based FPGA COTS boards, has joined the Altera Corp. Preferred Board Partner Program for OpenCL. BittWare's S5-PCIe-HQ (S5PH-Q) PCIe COTS board is optimized for the most current Altera devic ... read more |
| Category: News: News Archive 2013: |
| Cadence Introduces the Tempus Timing Sign-off Solution |
May 20, 2013 -- In a move to ease and speed the development of complex ICs, Cadence Design Systems, Inc. today introduced the Tempus Timing Sign-off Solution, a new static timing-analysis and -closure tool designed to enable system-on-chip ... read more |
| Category: News: News Archive 2013: |
| Fourth Multicore Challenge Now Open for Registration |
May 20, 2013 -- Taking place in Bristol UK on June 12, this year the conference, sponsored by Test and Verification Solutions, Ltd. (TVS), will focus on heterogeneous systems with three main themes of heterogeneous architectures, low power ... read more |
| Category: News: News Archive 2013: |
| Getting Started with SmartFusion2 Using IAR Embedded Workbench Featured |
May 16, 2013 -- Join IAR Systems for a one-hour webinar providing an introduction of IAR Embedded Workbench and how it can be used to write programs running for the ARM Cortex-M3 core within SmartFusion2 SoC FPGAs. The webinar will start with a q ... read more |
| Category: Vendor Webcasts: Upcoming Webcasts: |
| How to Do Functional Tests on I2C and SPI Monitors with JTAG Explored in eBook from ASSET InterTech |
May 16, 2013 -- A new eBook from ASSET InterTech explains how the structural test methodology based on the IEEE 1149.1 boundary scan standard, known as JTAG, can apply functional tests to I2C and SPI system monitors during prototype-board ... read more |
| Category: News: News Archive 2013: |
| Imec and GlobalFoundries Collaborate to Advance High-Density Memory Technology |
May 21, 2013 -- Imec and GlobalFoundries announced today that they have expanded joint development efforts to advance STT-MRAM (spin-transfer torque magneto-resistive RAM) technology.
The first IC manufacturer to jo ... read more |
| Category: News: News Archive 2013: |
| Mentor and Tezzaron Optimize Calibre 3DStack for 2.5/3D-ICs |
May 20, 2013 -- Mentor Graphics Corp. and Tezzaron Semiconductor Corp. today announced they are collaborating to integrate the Mentor Calibre 3DStack product into Tezzaron's 3D-IC offerings. The new integration will focus ... read more |
| Category: News: News Archive 2013: |
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