More SOCcentral news articles on FPGAs/CPLDs/PLDs (back to top) |
| Innopower Unveils iPaaS IP Program (8/25/2010) |
| OCP-IP Provides Virtual Platform Leveraging Advanced OCP SystemC TLM Modeling Kit (8/25/2010) |
| Synopsys Announces Immediate Availability of DesignWare MIPI M-PHY IP in 40-nm Process Technology (8/25/2010) |
| DapTechnology's 1394b FireLink Extended IP Boosts Download Performance on Ampex MiniR700 Solid State Data Recorder (8/24/2010) |
| HDL Design House Announces HVT M25PX VITAL Behavioral Model (8/24/2010) |
| Intilop Announces Acceptance of TCP/IP Off-Load Engine Silicon IP By a Major Financial Institution (8/24/2010) |
| SiliconBlue Ships Highest Logic Capacity FPGA in 6x6-mm Footprint Package (8/24/2010) |
| Lyric Semiconductor Launches New Kind of Computing with Probability Processing Circuits (8/17/2010) |
| Actel Releases Windows 7 Compliant Libero IDE (8/16/2010) |
| Aizyc Technology Announces Silicon-Proven SDIO 3.0 Host IP Core (8/16/2010) |
| Dini Group's DN2076k10 Emulates Up to 37 Million ASIC Gates for High-Speed Prototyping (8/16/2010) |
| InPA Systems Targets Active Debug for Rapid Prototyping (8/16/2010) |
| Lattice Announces Improved Synthesis and Power Optimization in CPLD Design Tools (8/16/2010) |
| Power.org Unveils New Power Architecture Silicon Roadmap (8/16/2010) |
| Rochester Electronics Provides Continuous Support of Altera's FPGAs (8/16/2010) |
| Synopsys Launches DesignWare USB Software Alliance Program (8/16/2010) |
| VarioTAP In-System Emulation Technology Supports ARM11 Core (8/16/2010) |
| Analog Devices Collaborates with Altera to Streamline Wireless Infrastructure System Development (8/11/2010) |
| Avalon's 2D FEC Enables Reduced Chip Size, Increased Power Savings (8/11/2010) |
| SiliconReef Acquires Chipus High-Performance Analog IP Licenses (8/11/2010) |
| Synopsys Adds TDD Support to LTE Model Library (8/11/2010) |
| Synopsys and Lattice Renew OEM Relationship for FPGA Synthesis Software (8/11/2010) |
| WaveFormer Lite Generates Mixed-Signal HDL Test Benches for All FPGA Design Flows (8/11/2010) |
| Aldec Announces Phase-Based Linting Methodology (8/9/2010) |
| Cadence Aligns Workforce to Deliver On EDA360 Vision (8/5/2010) |
| MoSys, Radiocomp and GDA Technologies Partner to Deliver CPRI and OBSAI Compliant Wireless SerDes IP Solution (8/5/2010) |
| NI Extends LabVIEW FPGA and C Series I/O with New High-Channel-Count Expansion Chassis (8/5/2010) |
| Northwest Logic Verifies Compatibility of Its IP Cores with Aldec RTL Simulators (8/2/2010) |
| IP Cores Announces a MACsec Security Processor IP Core (7/29/2010) |
| Actel Announces New FlashPro4 Programmer (7/28/2010) |
| Altium to Partner with FPGAworld at Munich Premier (7/28/2010) |
| CSR Expands Audio Expertise with Acquisition of APT (7/28/2010) |
| DVCon 2011 Announces Call for Paper and Panel Abstracts and Tutorial Proposals (7/28/2010) |
| EnSilica Declares "Open Season" On the 8051 (7/28/2010) |
| QuickLogic Announces Frame Buffer Solution to Extend Battery Life of Consumer Devices (7/28/2010) |
| Synopsys First to Deliver High-Performance Audio IP in 40-nm and 55-nm Process Technologies (7/28/2010) |
| Virage Logic's New ARC Sound AS221BD Dual-Core Processor Targets Blu-ray Audio (7/28/2010) |
| Xilinx Improves Design Flow for Partial-Reconfiguration FPGA Technology with ISE Design Suite 12.2 (7/28/2010) |
| Jasper DFI Formal Verification Proof Kits Now Available (7/27/2010) |
| Pico Computing Announces Signal Processing Library (7/27/2010) |
| Altera's Stratix V FPGAs Provide RLDRAM 3 Memory Support (7/26/2010) |
| IP Cores Announces IPsec Security Processor IP Core (7/26/2010) |
| Pico Computing Accelerates Cracking of NTLM Authentication Protocol by 500X (7/23/2010) |
| CEA-Leti Unveils Low-Power Reconfigurable Multicore Chip for Software-Defined Radio and Cognitive Radio (7/22/2010) |
| Aeroflex Gaisler Introduces MIL-STD-1553B IP Core (7/21/2010) |
| Cadence and ARM Collaborate to Create ARM-Optimized System Realization Solution (7/21/2010) |
| EnSilica's eSi-RISC Embedded Processors Validated for Mentor Graphics' Precision Synthesis FPGA Design Flow (7/21/2010) |
| Posedge Announces Small, Fast SDIO 3.0 Device Controller (7/21/2010) |
| Actel's CoreFIR v4.0 Delivers Configurable Digital Filter Generation for RTAX-DSP with On-Chip Math Blocks (7/19/2010) |
| Actel's Radiation-Tolerant Flash-Based FPGAs Now Qualified for Spaceflight Systems (7/19/2010) |
| Actel's RTAX-DSP FPGAs Achieve MIL-STD-883 Class B Qualification (7/19/2010) |
| CoreFFT v4.0 Now Available for Actel's RTAX-DSP FPGAs (7/19/2010) |
| Lattice Expands Reference Design Portfolio for MachXO and ispMACH 4000ZE PLDs (7/19/2010) |
| Xilinx Launches High-Density, Rad-Hard Reconfigurable FPGA for Space Applications (7/19/2010) |
| Cypress and Future Electronics Jointly Develop Low-Cost PSoC 3 Development Board (7/16/2010) |
| Tabula Builds New Sales Rep Organization (7/16/2010) |
| MoSys and Northwest Logic Offer Integrated PCI Express and DDR3 Solutions (7/14/2010) |
| Algotronix Announces XTS-AES IP Core for Storage Applications (7/13/2010) |
| EDA Consortium Reports Revenue Increase for Q1 2010 (7/13/2010) |
| GSA Announces Infrastructure to Ease Third-Party IP Licensing Process for Semiconductor Industry (7/13/2010) |
| GSA Awareness Campaign Emphasizes Global Opportunities for the European Semiconductor Industry (7/13/2010) |
| Silicon Image Introduces New RAID IP Core Based on Production-Proven SteelVine Technology (7/13/2010) |
| Altera Ships Lowest Power FPGAs with 6.375-Gbps Transceivers (7/12/2010) |
| Arithmetic Processing IP Core for MP3 Decoders Feature Smallest Circuit Size and Lowest Power Consumption (7/12/2010) |
| ARM Launches RVDS v4.1 and DSTREAM (7/12/2010) |
| IAR Systems Incorporates Power Debugging as Standard in IAR Embedded Workbench (7/12/2010) |
| SiliconBlue Ships 6.25-mm˛ mobileFPGA for Mobile Handsets (7/12/2010) |
| IP Cores Ships High-Speed Forward Error Correction IP Core (7/9/2010) |
| MIPS Technologies Teams with ETRI to Encourage SOC Design Innovation in Korea (7/9/2010) |
| Worldwide Semiconductor Revenues Will Increase to $295 Billion in 2011; Surpass $340 Billion in 2014 (7/9/2010) |
| Altera's Quartus II Software Version 10.0 Delivers Performance and Productivity for High-End FPGAs (7/6/2010) |
| IP Cores Ships Compression/ Encryption Combo IP Core (7/6/2010) |
| Lattice and Helion Provide Full HD HDR Color Pipe for Video Security and Surveillance Applications on Lattice FPGAs (7/6/2010) |
| Sundance Introduces Its Latest OFDM FPGA IP Core Based On 802.11a/g/n (7/6/2010) |
| SynaptiCAD's VeriLogger Supports Encrypted Models from Actel, Altera, and Xilinx (7/1/2010) |
| Global Semiconductor Alliance and VLSI Research Announce Partnership (6/30/2010) |
| IC Manage Releases 2nd Annual Global Design Data Management Survey Results (6/30/2010) |
| Tensilica Adds FLAC Decoder to HiFi Audio Codec Library (6/30/2010) |
| Virage Logic Broadens IP Offerings with New Portfolio of Production-Proven Processor Peripheral Cores (6/30/2010) |
| BittWare's ATLANTiS FrameWork Simplifies FPGA Integration and Implementation (6/29/2010) |
| Lattice and Affarii Technologies Offer Complete Remote Radio Head Hardware Solution for Wireless Infrastructure (6/29/2010) |
| ASICS World Services Achieves Compliance Certification for SATA Host IP Core (6/28/2010) |
| Lattice Semiconductor Introduces New Software for Low-Power, Cost-Sensitive FPGA Applications (6/28/2010) |
| Elliptic Technologies Upgrades DRM Solution to Latest DTCP-IP Standard (6/24/2010) |
| nSys Announces Functional Coverage Test Suites for Upcoming PCI Express 3.0 Specification (6/24/2010) |
| Tensilica HiFi Audio DSP Becomes First IP Core Approved for Dolby MS10 Multistream Decoder (6/24/2010) |
| Virage Logic Releases Major Update of the Open Source GNU and Linux Toolchains for Its ARC Processor Cores (6/24/2010) |
| Actel Announces Power Management Solution for SmartFusion Intelligent Mixed-Signal FPGAs (6/23/2010) |
| Altera Delivers Single-Chip Solution for HD WDR Surveillance Cameras (6/23/2010) |
| Arasan Chip Systems Announces Highly Integrated 10G Ethernet MAC IP Core (6/23/2010) |
| IP Cores Ships High-Speed Loss-Less Compression Core (6/23/2010) |
| Aldec Supports OVM and UVM in Riviera-PRO (6/21/2010) |
| Cadence Completes Acquisition of Denali (6/21/2010) |
| Xilinx 7 Series FPGAs Slash Power Consumption by 50% and Reach 2 Million Logic Cells on Scalable Architecture (6/21/2010) |
| Xilinx Spartan-6 FPGA Support MECHATROLINK-III Interface for Low-cost, High-speed Factory Automation Networks (6/21/2010) |
| Altera Starts Production Shipments of Highest Density Member of Its Stratix IV FPGA Family (6/17/2010) |
| ARM, IBM, Samsung, GlobalFoundries and Synopsys Announce Delivery of 32-/ 28-nm HKMG Vertically Optimized Design Platform (6/17/2010) |
| CAST H.264 Video Encoder IP Core Now More Flexible, Faster, and Easier to Integrate (6/17/2010) |
| GiDEL Announces Availability of TotalHistory for ASIC Prototyping and FPGA Debug (6/17/2010) |
| S2C Announces 4th Generation Rapid SOC Prototyping Solution (6/17/2010) |
| SiliconBlue's New iCEcube2 Development Tool Enables the Creation of Innovative Functions that Compliment Mobile Chipsets (6/17/2010) |
| ARM Accelerates Software Development on Hardware Assisted Verification Systems with VSTREAM (6/14/2010) |
| Avery Design Enhances Insight for Reachability Analysis, Lower Power Verification, and RT-Level DFT Analysis (6/11/2010) |
| Cyclic Design's Enhanced G14X BCH ECC IP Supports 64-bit Error Correction for NAND Flash Applications (6/11/2010) |
| GateRocket Adopts IVerifySpec from Agnisys for RocketDrive Development (6/11/2010) |
| Imagination Technologies Announces PowerVR SGX544MP Multiprocessor Graphics IP (6/11/2010) |
| Intersil's New Point-of-Load Power Solution Now Approved for Xilinx's Spartan-6 and Virtex-6 FPGA Multi-Gigabit Transceiver Evaluation Kits (6/11/2010) |
| Menta and LIRMM Launch Manufacturing of the First RAM-based FPGA (6/11/2010) |
| Oasys Design Systems Announces Multi-Year Strategic Chip Synthesis Technology License with Xilinx (6/11/2010) |
| Paradigm Works Announces SystemVerilog FrameWorks Template Generator Support for UVM (6/11/2010) |
| Synopsys to Acquire Virage Logic (6/11/2010) |
| CAST 80251 Processor IP Core Runs Legacy and New Code Up to 24X Faster (6/8/2010) |
| Chips&Media Adds VP8 On Its New BODA9 CODA9 (6/8/2010) |
| Evatronix Facilitates Evaluation of Its JPEG 2000 Encoder with Online Demo Application (6/8/2010) |
| Imperas Releases Fast Models of PowerPC Processors Through Open Virtual Platforms (OVP) Initiative (6/8/2010) |
| Latest Release of Aldec's Riviera-PRO Supports OVM/UVM (6/8/2010) |
| Tensilica Expands Wireless Baseband Business Unit (6/8/2010) |
| Xylon Introduces Low-Volume IP Licensing Program for Xilinx FPGAs (6/8/2010) |
| Actel Delivers Free IP Cores Bundle and RTL Package Option with Standard Software Packages (6/7/2010) |
| Calypto's SLEC 5.0 Release Includes New Formal Verification Technology for Complex Loop Handling (6/7/2010) |
| Cypress Introduces New Development Platform for PSoC 5 Programmable SOC Architecture with ARM Cortex-M3 Processor (6/7/2010) |
| Jasper Unviels New Data-Sharing Capabilities in ActiveDesign and JasperGold (6/7/2010) |
| Low-Cost Brevia Development Kit Accelerates Application Development for LatticeXP2 FPGA Family (6/7/2010) |
| Mentor Graphics Underscores Support for OVM and Extends Support to UVM Across Multiple Products (6/7/2010) |
| National Instruments Announces Module for Camera Link FPGA Image Processing (6/7/2010) |
| OneSpin Solutions Enhances 360 MV for Safe, Exhaustive 4-State Formal Analysis and Verification (6/7/2010) |
| PLDA Introduces PCI Express 3.0-Based IP for ASIC and FPGA (6/7/2010) |
| SiliconBlue Completes $15M Series C Preferred Stock Financing (6/7/2010) |
| Xilinx Virtex-6 and Spartan-6 FPGA Connectivity Targeted Reference Designs Support PCI Express-Compliant Designs (6/7/2010) |
| Avnet Memec and Actel Launch SmartFusion SpeedWay Workshops (6/4/2010) |
| DAC's Embedded/ SOC Enablement Day Focused on Embedded Processor-Based SOCs (6/4/2010) |
| Management Day at 47th DAC: Decision-Making at the Intersection of Business and Technology (6/4/2010) |
| Synopsys Announces Synphony HLS Support for Xilinx Virtex-6 FPGAs (6/4/2010) |
| Synopsys Press Publishes "The Ten Commandments for Effective Standards" (6/4/2010) |
| Vennsa Technologies Unveils OnPoint Software to Automate Debugging, Error Localization (6/4/2010) |
| Gartner Says Worldwide Semiconductor Revenue to Grow 27% in 2010 (6/3/2010) |
| Mentor Graphics Introduces Precision Rad-Tolerant Product for Advanced Radiation Effects Mitigation (6/3/2010) |
| MoSys and Sarance Partner to Deliver Complete 40 Gigabit and 100 Gigabit Ethernet and Interlaken Solutions (6/3/2010) |
| Celebrate Accellera’s 10 Years of Standards Excellence at 47th DAC (6/2/2010) |
| Meet Leading IP Suppliers at DAC During ChipEstimate.com IP Talks! (6/2/2010) |
| Altera's Stratix IV GT FPGA Selected by NEC for Use in Advanced 100G Transponder Card for DWDM System (6/1/2010) |
| CoFluent Design Adds Embedded C Code Generation to Its UML and systemC-Based Modeling and Simulation Toolset (6/1/2010) |
| GateRocket Adds Xilinx Virtex-6 Support to RocketDrive FPGA Verification and Debug Solution (6/1/2010) |
| Lattice Expands Hot-Swap Application Coverage for Power Manager Devices (6/1/2010) |
| Lattice Semiconductor Launches Free "Power 2 You!" Seminar Series (6/1/2010) |
| Mentor Graphics 0-In Formal Version 3.0 Brings New Level of Automation to Formal Verification (6/1/2010) |
| Mentor Graphics Releases 0-In CDC Version 3.0 to Support Verification Needs of Larger, More-Complex Designs (6/1/2010) |
| MIPS Technologies Announces Symmetric Multiprocessing Support for Android Platform on MIPS-Based SOCs (6/1/2010) |
| Panels at 47th DAC of Interest to Both EDA Developers and Design Community (5/31/2010) |
| Digital Imaging Core Now Available from Darbeevision (5/28/2010) |
| Sapient Systems Introduces Software for IC Industry Decision Makers (5/28/2010) |
| Si2 to Host "Design for Manufacturability Coalition Workshop" at DAC 2010 (5/28/2010) |
| CAST Reference Design System Simplifies H.264 Video Compression Evaluation and Analysis (5/26/2010) |
| Duolog's Socrates Chip-Integration Hub Supports Cadence's EDA360 Vision (5/26/2010) |
| Menta Unveils eFPGA Creator Development Suite to Create Customizable Programmable Logic Architecture (5/26/2010) |
| Virage Logic Expands Suite of Certified, Fully Optimized Audio Codecs, Underscoring Investment In ARC Processors (5/26/2010) |
| Altium Adds Aldec FPGA Simulation Technology to Altium Designer (5/25/2010) |
| Innopower Announces Availability of Faraday USB 3.0 Physical Layer IP (5/25/2010) |
| Tabula’s CTO Steve Teig to Speak During DAC Luncheon (5/25/2010) |
| Compaan Design Releases HotSpot Parallelizer for ISO C (5/24/2010) |
| Evatronix Introduces Ultra-Fast Intel 80C251-Compatible Microcontroller IP Core (5/24/2010) |
| Rapid Bridge LiquidIP Now Available as Part of Cadence Open Integration Platform (5/24/2010) |
| IPextreme to Provide ColdFire IP Cores as Standard 32-Bit Processor for Tabula ABAX 3PLDs (5/20/2010) |
| Mentor Graphics Announces New FPGA Synthesis Innovation in Precision Synthesis 2010a Release (5/20/2010) |
| Analogix Announces Availability of DisplayPort 1.2 HBR2 5.4-Gbps Products (5/19/2010) |
| Forte Unveils Cynthesizer Ultra, Next-Generation High-level Synthesis (5/19/2010) |
| MoSys and PLDA Partner to Deliver Complete PCI Express 2.0 and 3.0 IP Solutions (5/19/2010) |
| VeriSilicon Announces Support for WebM on ZSP Digital Signal Processor Cores and SOCs (5/19/2010) |
| Actel Releases New ARINC 429 Development Kit (5/18/2010) |
| Alizem Releases New COTS Motor Control IP for Pump and Fan Applications (5/18/2010) |
| DAC Announces 8th Annual ESL Symposium (5/18/2010) |
| eASIC Nextreme Used for Hardware Validation of Microsoft RemoteFX Technology (5/18/2010) |
| Wipro Technologies Selects Lattice MachXO PLDs for New Server Platforms (5/18/2010) |
| Cadence to Acquire Denali (5/14/2010) |
| Actel's New Core1553 Development Kit Gives Access to MIL-STD-1553B Bus Evaluation System Based on Fusion Mixed-Signal FPGAs (5/13/2010) |
| CAST Offers 12-bit JPEG Extended Sequential, DICOM-Compatible IP Core (5/13/2010) |
| Impulse C Support Enhanced for DRC’s Accelium, Xilinx-based, Acceleration Cards (5/13/2010) |
| Lattice Semiconductor Plans SRIO Interoperability with Cavium Networks' Octeon II Processors (5/13/2010) |
| Xilinx and Hitachi Announce New Virtex-6 FPGA-Based LogicBench Series Platform for System-Level Design Verification in Japan (5/13/2010) |
| Empirix Cuts FPGA Development Time with GateRocket (5/10/2010) |
| NextOp Announces BugScope Assertion Synthesis for Progressive, Targeted Verification (5/10/2010) |
| Nominations Requested for EDA Industry's Prestigious Phil Kaufman Award (5/10/2010) |
| OCP-IP Delivers IEEE1685 OCP Vendor Extensions Fully Compatible with IP-XACT 1.4 (5/10/2010) |
| eASIC eTools 8.1 Design Suite Reduces Design Time by 40% (5/7/2010) |
| Evatronix Introduces a 65C02-Compatible Microprocessor IP Core (5/7/2010) |
| Synopsys Unveils Ethernet Controller IP with New Audio Video Bridging Feature (5/7/2010) |
| Microtronix Introduces Scatter Gather DMA Engine for Altera PCIe Hard IP Cores (5/3/2010) |
| SIA Reports March Chip Sales Grew by 4.6% Month-on-Month (5/3/2010) |
| Synopsys Launches Industrys First MIPI DigRF v4 IP (5/3/2010) |
| Xilinx ISE Design Suite 12 Enables Up to 30% Dynamic Power Reduction with Intelligent Clock-Gating Technology (5/3/2010) |
| New Synopsys Universal DDR Controllers Improve Performance and Reduce Cost of Embedded DRAM Interfaces (4/28/2010) |
| Xilinx Unveils New ARM-Based Processing Architecture (4/28/2010) |
| Actel's SmartFusion Intelligent Mixed-Signal FPGAs Target High-Complexity Motor-Control Solutions (4/27/2010) |
| Imagination's PowerVR VXD391 adds On2 VP6 and Real Video capabilities (4/27/2010) |
| QuickLogic Enhances User Experience with OLED Displays (4/27/2010) |
| Takumi Launches GV330 Dedicated Vector Graphics IP Core with Enhanced Rendering Performance and Functionalities (4/27/2010) |
| CebaTech Launches New CebaFlex FPGA-Based Board-Level Protocol Acceleration Subsystems (4/26/2010) |
| Cryptography Research and Actel Announce License Agreement Enhancing Security of Actel FPGAs (4/26/2010) |
| Intilop Delivers Highly Integrated TOE_FPGA-SOC-Platform to a Major Financial Institution (4/26/2010) |
| Lattice Announces "Power 2 You" Guide to Power Supply Management and Control (4/26/2010) |
| NEC Display Solutions Adopts Xilinx FPGAs for 3D-Capable Cinema Projectors (4/23/2010) |
| QuickLogic Announces Solution to Optimize Mobile System Power (4/22/2010) |
| Synopsys Announces Support for Actel's New SmartFusion Intelligent Mixed-Signal FPGAs (4/22/2010) |
| Tensilica Introduces Third-Generation ConnX 545CK 8-MAC VLIW DSP Core (4/22/2010) |
| EMA Now Offers FPGA Design and Simulation Bundles for OrCAD Users (4/20/2010) |
| Qualcomm Adopts GateRocket Solution to Address FPGA Complexity Challenges (4/20/2010) |
| Zocalo Tech Introduces Assertion-Based Verification Capabilities to Improve IP and Electronic Design Quality (4/20/2010) |
| Actel Announces Keil's Support of New SmartFusion Intelligent Mixed-Signal FPGA Family (4/19/2010) |
| Aldec Adds RMM Library and FPGA Primitive Support to ALINT (4/19/2010) |
| Altera Unveils 28-nm Stratix V FPGA Family (4/19/2010) |
| CoFluent Design Joins the Mathworks Connections Program (4/19/2010) |
| Cypress Unveils New PSoC 3 Family with Integrated Low-Power Programmable Digital Logic (4/19/2010) |
| Synopsys Introduces the HAPS-60 Series of Rapid Prototyping Systems (4/19/2010) |
| IP Cores Announces New Version of Its RSA Public Key Accelerator (4/15/2010) |
| CAST Offers First 12-bit JPEG Extended Sequential, DICOM-Compatible IP Core (4/14/2010) |
| CoreEL Launches Advanced Video Decoding Solutions (4/14/2010) |
| Express Logic ThreadX Available for Tensilica's New Third-Generation Diamond Standard Dataplane Processor Cores (4/14/2010) |
| Lattice Accelerates PCI Express System Design with New Low-Cost LatticeECP3 Development Kit (4/14/2010) |
| Mentor Graphics Extends DO-254 Platform Offering with Enhanced HDL Coding Standards (4/14/2010) |
| VarioTAP In-System Emulation Technology Expanded to Support Xilinx FPGA (4/9/2010) |
| IP Cores Ships New Version of Its SHA Family of Hash Cores (4/8/2010) |
| Nu Horizons Electronics Named Global Distributor for Lattice Semiconductor (4/8/2010) |
| OptNgn Releases High-Performance, Vendor Independent Downloadable 264 FFT FPGA Library Elements (4/8/2010) |
| CEVA Releases SATA3.0 IP for 6-Gbps SSD Applications (4/7/2010) |
| Cyclic Design Licenses G14 BCH ECC IP to Trident Microsystems (4/7/2010) |
| Synopsys DesignWare DDR multiPHY IP Supports Six DDR Standards In a Single PHY (4/7/2010) |
| Xilinx Helps University of Regensburg Launch the World's Most Power-Efficient Supercomputer (4/6/2010) |
| EDA Consortium Reports Decrease for 2009 But Sequential Fourth Quarter Gains (4/5/2010) |
| Intilop Releases New Fully Integrated FPGA-SOC-Platform with TOE, PCI Express and System Peripherals (4/5/2010) |
| Lattice Announces Updates and Enhancements to Its FPGA Design Tool Suite (4/5/2010) |
| Mentor Graphics ReqTracer Automates Requirements Tracking and Reporting for Electronic Design Projects (4/5/2010) |
| Synopsys' DesignWare SuperSpeed USB 3.0 IP Receives USB-IF Certification (4/5/2010) |
| Altera's Stratix IV GT FPGAs Interoperate Directly with 40G QSFP Optical Modules (4/1/2010) |
| CriticalBlue's Prism Supports MIPS Architectural Detail to Accelerate Selection, Use and Deployment of Most Appropriate Multicore/ Multithreaded Platform (4/1/2010) |
| Imperas and OVP Initiative Release Full Support for MIPS Technologies' MIPS32 M14K Processors (4/1/2010) |
| Silicon Image Reorganizes to Bring Increased Focus to Its Products and Intellectual Property Businesses (4/1/2010) |
| SiliconBlue Selects Synopsys as FPGA Synthesis Partner for Its iCE65 mobileFPGA Family (4/1/2010) |
| Elliptic Technologies Offers Security Engine for Multicore SOC Designs (3/31/2010) |
| Parallel Engines Licenses Verific Verilog Parser Serves as Front End to Next-Generation Floorplanner (3/31/2010) |
| Target Compiler Technologies Signs Acetronix As Agent for Korea (3/31/2010) |
| Cypress Introduces PSoC 3 and PSoC 5 Device Selection Tool Helps Designers Customize PSoC Solutions (3/30/2010) |
| Altera Rolls Out Production Shipments of Low-Cost, Low-Power Cyclone IV FPGAs (3/29/2010) |
| EnSilica Launches Major New Version of Its eSi-RISC Development Suite (3/29/2010) |
| IAR Systems Supports Actel's New SmartFusion Intelligent Mixed-Signal FPGAs (3/29/2010) |
| MoSys Acquires MagnaLynx (3/29/2010) |
| Pigeon Point Systems Announces IPMC and Carrier IPMC BMR Starter Kits Using SmartFusion Mixed-Signal FPGAs (3/29/2010) |
| Pigeon Point Systems Delivers New MMC Management Solution Using SmartFusion Intelligent Mixed-Signal FPGAs (3/29/2010) |
| QuickLogic First to Market Display Controller Solution Supporting 60-fps Content Refresh Over MDDI Type 2 (3/29/2010) |
| Altera and Apical Deliver HD Wide Dynamic Range FPGA Solution for Surveillance (3/24/2010) |
| Avnet Spartan-6 FPGA DSP Development Kit Jump Starts DSP Designs (3/24/2010) |
| IP Cores Ships an AES Encryption Core Supporting the EAX' Encryption Mode of ANSI C12.22 (3/24/2010) |
| Virage Logic Introduces MIPI D-PHYs and Controllers on 40LP Process (3/24/2010) |
| Synopsys Completes Acquisition of CoWare (3/23/2010) |
| The MathWorks and Mentor Graphics Outline Joint DO-254 Workflow for Model-Based Design (3/23/2010) |
| 1394 Trade Association Issues Comprehensive FireWire Reference Tutorial for IEEE 1394 Standard (3/22/2010) |
| Vitesse's New Forward Error Correction Technology Eases Migration to 100G (3/22/2010) |
| Evatronix Optimizes Its I2S Audio Interface Controller by Adding TDM Support and Single Channel Operation (3/16/2010) |
| Parallel Engines Focuses on Merging of EDA and Semiconductor/ IP Integration (3/16/2010) |
| Tabula Launches ABAX Family of 3-D Programmable Logic Devices (3/16/2010) |
| Tensilica Introduces 3rd Diamond Standard Controllers Optimized for Low-Power, High-Performance Applications (3/16/2010) |
| Noesis Technologies Releases Fully Configurable N-point FFT/ IFFT Core (3/15/2010) |
| Tier Logic Announces 3D-Based Technology for FPGAs and ASICs (3/11/2010) |
| nSys Announces Functional Coverage Test Suites for Major Standards/ Protocols (3/9/2010) |
| Posedge Announces High- Speed, High-Performance, and Low-Gate-Count SD/ SDIO/ eMMC Host Controller IP (3/9/2010) |
| Altera's Stratix IV FPGAs Pass Interlaken Interoperability Test (3/8/2010) |
| Arasan Chip Systems Releases NAND Flash File System Software (3/8/2010) |
| ARM AMBA 4 Specification Maximizes Performance and Power Efficiency (3/8/2010) |
| Carbon Unveils New Generation of ARM Models with Availability of Mali Models (3/8/2010) |
| Micrium Supports Actel SmartFusion Devices (3/8/2010) |
| Actel Introduces SmartFusion Devices - FPGAs with ARM Cortex-M3 Processor and Programmable Analog (3/4/2010) |
| Actel Releases Comprehensive Development Environment and Ecosystem for SmartFusion Intelligent Mixed-Signal FPGAs (3/4/2010) |
| CSEM Introduces a New Generation of Ultra-Low-Power DSP RISC Cores (3/4/2010) |
| iSine Releases Extreme ECC for NAND Flash SOC's Optimized for ASIC and Xilinx FPGA Implementation (3/4/2010) |
| Xilinx and Inova Semiconductors Simplify Design Integration of High-Bandwidth Video Connections for Automotive Applications (3/4/2010) |
| Xilinx Expands Automotive Silicon Portfolio with Spartan-6 FPGAs Optimized to Reduce System Cost (3/4/2010) |
| Noesis Technologies Releases NIST FIPS-197 Compliant Low-Power AES IP Core (3/1/2010) |
| Tabula Introduces Spacetime 3-D Programmable Logic Architecture (3/1/2010) |
| Duolog Tools Auto-Generate OVM Verification Environment (2/25/2010) |
| European SystemC User Group Meeting Co-Located with DATE 2010 (2/25/2010) |
| ExpertIO Announces PCI Express System Verification Component (2/25/2010) |
| Altera Transitions 40-nm Arria II GX FPGAs to Production (2/23/2010) |
| Avery Design Systems Announces AMBA AXI and AHB Verification Solution (2/23/2010) |
| CoWare SPW Boosts Signal Processing Prototyping for Advanced Wireless Systems (2/23/2010) |
| GateRocket Enhances FPGA Debug Solution with New Features to Reduce Design Bring-up Time by 50% or More (2/23/2010) |
| Xilinx Picks 28-nm High-Performance, Low-Power Process to Accelerate Platforms for Driving the "Programmable Imperative" (2/23/2010) |
| ARM Launches Cortex-M4 Processor for High-Performance Digital Signal Control (2/22/2010) |
| Denali Software Delivers 40/100Gbit Ethernet Verification IP Solution (2/22/2010) |
| OneSpin Announces Customizable Integration Between 360 MV Verification Solution and Platform LSF Infrastructure (2/22/2010) |
| OSCI Announces Public Review for Configuration Requirements of Configuration, Control & Inspection (CCI) Standardization Effort (2/22/2010) |
| OVP Releases High-Performance Models of NEC Processors (2/22/2010) |
| OVP Releases Reference Virtual Platform of ARM Model Running Linux Under SystemC/ TLM-2.0 (2/22/2010) |
| Samsung Electronics and Xilinx Announce Full Production Qualification for Spartan-6 FPGA Family on 45nm Low-Power Process Technology (2/22/2010) |
| SoftJin Announces High Performance JPEG Encoder and Decoder IP (2/22/2010) |
| e2v’s New 10-bit, 3-Gsps Demultiplexer (DMUX) Eliminates Gigahertz Data-Rate Bottleneck (2/17/2010) |
| Elliptic Technologies Offers Solution to Implementing Asymmetric or Public Key Cryptography (2/17/2010) |
| Vennsa Technologies Picks Verific Design Automation’s Front-End Software (2/17/2010) |
| Athena Group Delivers Powerful 3GPP LTE Multi Radix FFT Processor Core (2/15/2010) |
| CEVA Unveils Multipurpose Programmable HD Video- and Image-Processing Platform for Connected Multimedia Devices (2/15/2010) |
| Eureka Technology Supports PLB Bus Interface for Most of Its IP Cores (2/15/2010) |
| MIPS Technologies and SySDSoft Partner to Enable LTE on MIPS Architecture (2/15/2010) |
| SiliconBlue Enables Differentiated Mobile Broadband Products with New P-Series mobileFPGA Devices (2/15/2010) |
| Avnet Virtex-6 FPGA DSP Development Kit Jump Starts DSP Designs (2/10/2010) |
| Bluespec Delivers Plug-and-Play Library for Algorithm and Datapath Design (2/9/2010) |
| CoWare Teams with Xilinx to Accelerate LTE Basestation Design (2/9/2010) |
| CEVA Introduces Comprehensive Partner Program for LTE, WiMAX and SDR Wireless Communications Solutions (2/8/2010) |
| CEVA's New LTE Software Library Accelerates 4G Modem Development (2/8/2010) |
| IP Cores Announces Family of Low-Latency AES/GCM IP Cores Supporting IEEE 802.11ad and WiGig Standards (2/5/2010) |
| New MEN Micro 3U CompactPCI Board First to Combine Intel Atom Technology with Onboard FPGA (2/5/2010) |
| Posedge Announces ONFI-2.2 Compliant Universal Flash Controller IP Core (2/5/2010) |
| Cyclic Design Releases Advanced BCH Error Correction IP for Next-Generation NAND Flash Applications (2/4/2010) |
| Altium Adds High-Performance, Low-cost Option to Its NanoBoard 3000 Range (2/3/2010) |
| IP Cores Announces Update of Its Elliptic Curve Crypto Accelerator (2/3/2010) |
| SiSoft Announces Multiple Design Kits for Quantum Channel Designer (QCD) Serial Link Analysis Software (2/3/2010) |
| Altera Unveils Innovations for 28-nm FPGAs (2/2/2010) |
| Bosch Security Systems Selects Synfora's PICO C Synthesis Tool to Accelerate FPGA Development (2/2/2010) |
| Cypress and Keil Team Up to Deliver High-Performance Compiler Options for Cypress's New PSoC 3 and PSoC 5 Architectures (2/2/2010) |
| Evatronix and CMP Collaborate to Provide Universities and Research Laboratories with Advanced IPs (2/2/2010) |
| Intilop Announces New Development Platform Based on Xilinx V5 FPGA for Its TCP-Off-load Engine SOC IP (2/2/2010) |
| Lattice Semiconductor and eVision Systems to Serve the Video and Surveillance Market In Central Europe (2/2/2010) |
| Actel Announces Compliance with Quality Management Standards SAE/AS9100 and ISO 9001 (2/1/2010) |
| Agnisys Announces Support for OVM Register Package in IDesignSpec (2/1/2010) |
| Synfora Extends Support for C++ in PICO High-Level Synthesis Tool (2/1/2010) |
| Evatronix Software Driver Supports Its ONFi 2.2-Compatible NAND Flash Memory Controller (1/27/2010) |
| Arasan Chip Systems Strengthens Engagement in Japan (1/25/2010) |
| ARM-Based Processors to Overtake x86 in Ultra-Mobile Devices in 2013 (1/25/2010) |
| Nallatech Completes First Customer Shipment of 10Gb Ethernet PCI Express FPGA Accelerator Card (1/25/2010) |
| NXP and Intrinsic-ID Collaborate On Chip Security (1/25/2010) |
| Actel's Low-Power FPGAs Fly On Boeing's 787 Dreamliner (1/20/2010) |
| Ukalta Engineering Introduces FPGA-Based Fading-Channel Simulators (1/20/2010) |
| PICO High-Level Synthesis Platform Produces Quality of Results Comparable to Hand-Coded RTL (1/19/2010) |
| EDA Consortium Reports Industry Revenue Down in Third Quarter 2009 (1/18/2010) |
| Intilop Announces Xilinx FPGA Development Platform for Its TCP-Offload Engine IP (1/18/2010) |
| SynaptiCAD’s 64-Bit Verilog Simulator Now 30% Faster (1/18/2010) |
| Nominations for Accellera's 2010 Technical Excellence Award Due Monday, January 18 (1/13/2010) |
| Synopsys Announces DesignWare Protocol Analyzer for Verification of SuperSpeed USB 3.0-based Designs (1/13/2010) |
| Delivery of Virtex-6 LX760 Devices Extends FPGA Logic Capacity By More Than 2X (1/12/2010) |
| Synopsys Introduces SystemC TLM-2.0 SuperSpeed USB 3.0 Models (1/12/2010) |
| Alpha Data Releases New High-Performance Virtex-6 FPGA Based XMC Card (1/8/2010) |
| SoftJin Announces PAL-NTSC Encoder IP for Display Systems Including SDTV and HDTV (1/8/2010) |
| Xilinx Expands Programmable Advantage for Consumer Digital TV Displays (1/8/2010) |
| MIPS Technologies and Partners Accelerate SOC Design for Android-Based Devices (1/6/2010) |
| MIPS Technologies Collaborates with Adobe to Optimize Flash Player 10.1 for MIPS Architecture (1/6/2010) |
| Perfectus Announces Availability of SystemVerilog-Based OVM-Compliant PCI Express 3.0 Verification IP (1/6/2010) |
| SiliconBlue Technologies Expands iCE65 mobileFPGA Family (1/6/2010) |
| Xilinx-Based Hardware/ Software Co-simulation Accelerated on Dynalith/Impulse C-to-FPGA Prototyping System (1/4/2010) |
| Altium Adds Support for Xilinx Spartan-6 FPGA to Altium Designer (12/31/2009) |
| Digital Blocks Supports AMBA Interconnect on Xilinx FPGAs with Portfolio of IP Cores (12/31/2009) |
| Faraday to Transfer IP Business to Innopower (12/31/2009) |
| Ukalta Engineering Announces Ultra-Compact AWGN IP Library (12/28/2009) |
| Aldec Releases RTL Simulator with Enhanced Assertions and Xilinx SecureIP Support (12/24/2009) |
| Synfora Sponsors Educational Course on the "Fundamentals of ESL Synthesis" (12/24/2009) |
| Tensilica's ConnX D2 DSP Engine Wins EDN Top 100 Electronic Products Award for 2009 (12/24/2009) |
| eSilicon Takes Achronix 1.5GHz FPGA Design to Production (12/18/2009) |
| PetaLogix Launches Linux Development Environment Optimized for FPGA-Based Embedded Systems (12/18/2009) |
| New Fujitsu DAC Development Kit Adaptor Speeds System Prototyping, Reduces Risk and Cost (12/17/2009) |
| Virage Logic Introduces the Ultra Compact and Low Power ARC 601 32-Bit Microprocessor Core (12/16/2009) |
| Dolphin Integration Moving Ahead Toward Assertion-Based Verification with SLASH (12/14/2009) |
| Lattice Releases Development Platform for SerDes and Video Clock Distribution (12/14/2009) |
| Carbon Expands ARM IP Library to Include All Cortex Processors, AMBA AXI Fabric, and Peripherals (12/10/2009) |
| Maia EDA Launches New Automated Verification Tool (12/10/2009) |
| Mixel First to Market with Unified MIPI/ MDDI PHY IP Solution (12/10/2009) |
| New Cypress Kit Demonstrates Precision Analog of PSoC 3 Architecture Via Highly Integrated Voltmeter (12/9/2009) |
| New Xilinx Connectivity, Embedded, and DSP Kits Enable Increased Productivity for SOC Designs (12/9/2009) |
| New Xilinx Virtex-6 and Spartan-6 FPGA Connectivity Development Kits Include Northwest Logic DMA Engine IP (12/9/2009) |
| Altera Ships Stratix IV E FPGA Development Kit Featuring a 530K Logic Element FPGA (12/8/2009) |
| Chipworks Helps Leverage the Value of Systems Patents (12/8/2009) |
| Discretix joins ARM Solution Center for Android (12/8/2009) |
| Impulse Announces Customizable FPGA-Based Financial Feed Handling Solutions (12/8/2009) |
| Mentor Graphics Expands Questa Multi-View Verification Components Library to Support a Larger Set of Standard Protocols (12/8/2009) |
| Evatronix USB-IF Verified USB 3.0 Device Controller Achieves Over 430MBps (12/3/2009) |
| Actel Extends Core8051s Processor Support to RTAX, Axcelerator and Igloo Families (12/2/2009) |
| Altera's Stratix IV FPGAs to Power XtremeData's dbX Analytics Appliance (12/2/2009) |
| EVE's Latest Emulator Offers the Lowest Cost of Ownership in the Industry (12/2/2009) |
| Novelics, Chips & Media, and Posedge Join IPextreme Constellations (12/2/2009) |
| SiliconBlue Technologies First New FPGA Company to Ship in Production Volume in 20 Years (12/2/2009) |
| Spansion MirrorBit Flash Memory Now Available as Xilinx Spartan-6 FPGA Configuration Solution (12/2/2009) |
| Synfora Adds Support for Xilinx Virtex-6 and Spartan-6 FPGA Devices to PICO Algorithmic Synthesis Tool (12/2/2009) |
| Altium Releases Smart Prototyping Peripheral Board for NanoBoard Development Platforms (12/1/2009) |
| Evatronix Announces ONFi 2.2 High-Speed Interface Support to its NAND Flash Memory Controller (11/24/2009) |
| Altera Signs Distribution Agreement with Newark (11/23/2009) |
| Avnet Electronics Marketing to Distribute SP Devices' Products in North America (11/23/2009) |
| Lattice Announces Low-Cost FPGA with Serial RapidIO 2.1 Support (11/23/2009) |
| OCP-IP Releases OCP 3.0 Specification (11/23/2009) |
| New Cypress Kits Showcase Simplicity of LCD Segment Drive Design with Flexible New PSoC 3 Architecture (11/19/2009) |
| Actel Expands RTAX-DSP FPGAs with New Configurable DSP IP Cores (11/18/2009) |
| ARM Launches Solution Center to Foster Innovation and Speed Development of Android-Powered Devices (11/18/2009) |
| EnSilica Boosts Front-End IC Design Services with New eSi-RISC Configurable Processor Cores (11/18/2009) |
| Imagination Technologies Delivers HD Video Encoder IP Core with Full H.264 High-Profile Capability (11/18/2009) |
| Imagination's PowerVR VXD390 Adds Key New Functions to Maximize System-Level Performance (11/18/2009) |
| Verific Software Serves as Front-End to Oasys Design Systems RealTime Designer (11/18/2009) |
| Xilinx Simplifies Serial Digital Interface Development for High-Performance Professional Broadcast Audio and Video Systems (11/18/2009) |
| Aldec Announces Low-Cost Linux RTL and Gate-level Simulator (11/17/2009) |
| Arasan Chip Systems Releases SD/ SDIO 3.0 Combo Device Controller IP (11/17/2009) |
| Atrenta's SpyGlass-CDC Solution Boosts IP Integration Efficiency for Fujitsu Kyushu Network Technologies (11/17/2009) |
| FPGAs Speed Financial Derivative Risk Analysis By More than 1100X (11/17/2009) |
| Mitrionics and GiDEL Announce Joint Reseller Partnership for FPGA-Based Accelerated Computing Development Tools and PCI Cards (11/17/2009) |
| SynaptiCAD Offers a Free High-Performance Verilog 2001 Simulator (11/17/2009) |
| Actel Strengthens Fusion Mixed-Signal FPGA IP Offering for xTCA Platform Management Applications (11/16/2009) |
| Altera Delivers Serial RapidIO 2.1 IP Solution (11/16/2009) |
| Avnet, TI and Xilinx Launch Analog eLab Videocast Series (11/16/2009) |
| Lattice Announces Production Release of Highest Density LatticeECP3 FPGA (11/16/2009) |
| Posedge Annouces High-Performance 10-Gbps IEEE 802.1AE (MACsec) IP Core (11/13/2009) |
| Technical Presentations from North American SystemC Users Group Meeting Now Online (11/13/2009) |
| ANSYS Releases Engineering Knowledge Manager 2.0 for Simulation Data Capture, Reuse and Best Practices (11/12/2009) |
| GigOptix Acquires ChipX (11/12/2009) |
| Lattice and Beyond Semiconductor to Collaborate in Processor Compiler Tools Development (11/12/2009) |
| New Lattice FPGA Design Tool Suite Includes Support for High-Performance DDR Interfaces (11/12/2009) |
| Technical Presentations from North American SystemC Users Group Meeting Now Online (11/12/2009) |
| Arasan Chip Systems Releases ONFI 2.2 NAND Flash Controllers (11/11/2009) |
| Dolphin Integration Launches Cache Controller, Dynamically Self-Configured to Minimize Power Consumption (11/10/2009) |
| FPGA Cluster Accelerates Bioinformatics Application by 5000X (11/10/2009) |
| Lattice Announces Improved Hot-Swap Support for Power Management Devices (11/10/2009) |
| Lattice Updates Software Design Tools for Hot-Swap Control and Power Management (11/10/2009) |
| Arteris Enhances Network-on-Chip Offerings to Address Full Range of SOC Designs (11/9/2009) |
| Cypress Introduces New PSoC 1 Device with Enhanced Analog Performance (11/9/2009) |
| OSCI Introduces SystemC Synthesis Subset Draft Standard; Opens for Public Review (11/9/2009) |
| Pico Computing Powers HPC Accelerator Board with Xilinx Virtex-6 FPGAs (11/5/2009) |
| Virage Logic Completes Acquisition of ARC International (11/5/2009) |
| HDL Design House Announces I2S Soft IP Core (11/4/2009) |
| Noesis Technologies Releases ITU G.704 E1 Framer/ Deframer IP Core (11/4/2009) |
| Altera Boasts 2X to 3X Compile Time Advantage with Quartus II Software Version 9.1 (11/2/2009) |
| Altera's New Cyclone IV FPGA Expands Reach of Cyclone FPGA Series (11/2/2009) |
| Microtronix Introduces Video-over-IP Add-on Kit for Altera and Microtronix FPGA Development Boards (11/2/2009) |
| MIPS Technologies Introduces New Processor Cores with 32-bit Performance and Near 16-bit Code Size (11/2/2009) |
| Sital Announces Release of Mil-Std-1553 IP Core with PCI Interface (11/1/2009) |
| X-FAB to Moderate Panel at 7th Annual SOC International Conference Exploring Interrelationships Between Silicon and Biotechnology (10/28/2009) |
| Lattice and Affarii Deliver Low-Power, Low-Cost RRH Solution (10/27/2009) |
| Cypress Provides Solutions IP for New PSoC 3 Devices and PSoC Creator IDE (10/26/2009) |
| Altera Starts Production Shipments of FPGAs with Integrated 11.3-Gbps Transceivers (10/22/2009) |
| QuickLogic Announces Availability of Its ArcticLink II VX2 CSSP Solution Platform (10/22/2009) |
| QuickLogic Extends Battery Life with Display Power Optimizer (DPO) Proven System Block (10/22/2009) |
| Timesys Delivers a Comprehensive, Low-Cost Linux Solution for Altera's Nios II Embedded Processor (10/22/2009) |
| Altera Secures Designs with Cyclone III LS FPGA Development Kit (10/19/2009) |
| Intune Networks Selects Duolog's Bitwise Register Management Tool (10/19/2009) |
| Lattice Simplifies System Control Applications with MachXO Control Development Kit (10/19/2009) |
| Xilinx and ARM Announce Development Collaboration (10/19/2009) |
| EMA Partners with Aldec to Provide Cadence OrCAD Users a Complete FPGA Design Solution (10/16/2009) |
| Synopsys Introduces Synphony High-Level Synthesis (10/14/2009) |
| Altera Enhances the MAX II Family (10/12/2009) |
| Lattice Semiconductor and Epson Toyocom Provide Low-Cost, High-Frequency Differential Reference Clock Solution (10/12/2009) |
| Altera Licenses MIPS Technologies' MIPS32 Architecture (10/7/2009) |
| North American Engineering Student FPGA Competition Sign-Ups Open (10/5/2009) |
| Xilinx Spartan-6 FPGAs Enable PCI Express Compliant System Design for Low-Power, Low-Cost Connectivity Applications (10/5/2009) |
| Accellera Members Approve VIP Standard Best Practices Guide (10/2/2009) |
| ChipStart Offers a Subsystem Alternative for SOC System Management (10/2/2009) |
| Avnet Electronics Marketing Releases New Xilinx Spartan-6 FPGA Evaluation and Development Kits (10/1/2009) |
| Evatronix Introduces the Fast SD/ SDIO/ MMC Host Controller (10/1/2009) |
| Premier Farnell to Sell Altium'S New NanoBoard 3000 Series of FPGA-Based Development Boards (10/1/2009) |
| siXis Introduces Reconfigurable Computing Platform (10/1/2009) |
| Altera's Stratix IV GX FPGAs Move to Volume Production (9/23/2009) |
| ARM Makes Multi-Chip Debug Affordable In End Products (9/23/2009) |
| Arrow Electronics and Altera Make Soft-Core Processors Available on BeMicro Evaluation Boards (9/23/2009) |
| Evatronix Introduces Fast SD/ SDIO/ MMC Host Controller (9/23/2009) |
| Imagination Announces PowerVR Insider SDK 2.5 (9/23/2009) |
| Achronix Unveils 120-Gbps Reprogrammable Networking System (9/17/2009) |
| Arasan Chip Systems Adds IEEE 1588 PTP Support to Ethernet IP Core (9/17/2009) |
| ARM Announces 2GHz Capable Cortex-A9 Dual-Core Processor Implementation (9/17/2009) |
| Microtronix Boosts Performance of MDDR Memory Controller IP Core to 200MHz (9/17/2009) |
| Si2 Announces the 14th Si2/OpenAccess+ Conference (9/17/2009) |
| Toshiba Announces Availability of Free and Low-Cost Development Tools for ARM Microcontroller Families (9/17/2009) |
| Xilinx Extends Next-Generation Serial Connectivity Portfolio from Low-Cost Systems to 100-Gigabit Applications (9/17/2009) |
| IBM Announces Highest-Performance Embedded Processor for SOC Designs (9/16/2009) |
| Altera Unveils 820K-LE Stratix IV FPGA (9/15/2009) |
| Altium's New FPGA-based Development Board Simplifies Prototyping (9/15/2009) |
| Cypress Unveils High-Performance, Low-Power PSoC Programmable System-on-Chip Architectures (9/14/2009) |
| PSoC Creator Software Provides Design Environment for New Cypress PSoC 3 and PSoC 5 Architectures (9/14/2009) |
| Radiocomp Releases 4G Ready OBSAI RP3 v4.1 IP core for LTE, WCDMA and WIMAX (9/14/2009) |
| Xilinx FPGAs Enable TeamCast Digital TV and Mobile TV Modules for Professional Broadcast Systems (9/14/2009) |
| element14 Invites Engineers to "RoadTest" New Technologies from Freescale and Altera (9/13/2009) |
| SynaptiCAD Tools Import Xilinx Timing Information (9/10/2009) |
Magazine & Journal articles on FPGAs/CPLDs/PLDs (back to top) |
| Using Switched Capacitors to Create Programmable Analog Logic Blocks In Mixed-Signal Designs (Programmable Logic DesignLine) 8/18/2010 |
| Comparing AMBA AHB to AXI Bus Using System Modeling (Design & Reuse) 8/16/2010 |
| Data Storage Yields Increased Design Productivity (EDN Magazine) 8/16/2010 |
| FPGA Compilation On-Site or In the Cloud (Programmable Logic DesignLine) 8/16/2010 |
| IP Integration: Is It the Real System-Level Design? (EDN Magazine) 8/16/2010 |
| Reduce Embedded SOC Design Cost and Optimize IP Integration (Embedded Systems Design (embedded.com)) 8/16/2010 |
| Transaction Analysis and Debug Across Language Boundaries and Between Abstraction Levels (Design & Reuse) 8/16/2010 |
| ESL Synthesis: Tips for Implementing a Viable ESL-Synthesis Flow (EDN Magazine) 7/30/2010 |
| Protect Your goal with Post-Silicon Formal Verification (Design & Reuse) 7/30/2010 |
| Customized FPGA board for ASIC Prototyping: A Novel Approach with Pre-designed Blocks and Modular FPGA (Design & Reuse) 7/29/2010 |
| IP Re-Engineering and Design Methodology (Design & Reuse) 7/29/2010 |
| Give the People What They Want: HLS for RTL Verification (EDA DesignLine) 7/21/2010 |
| Web-Based IC Customization Revolutionizes Timing Circuits (Electronic Products) 7/1/2010 |
| Debug Will Get Your Attention, Sooner or Later (EDA DesignLine) 6/29/2010 |
| Time Is Right for Clockless Design (EDA DesignLine) 6/29/2010 |
| Path-Specific Derating to Reduce Timing Pessimism (EDN Magazine) 6/25/2010 |
| How to Make Virtual Prototyping Better than Designing with Hardware: Part 2 - The Importance of Testability In Virtual Prototyping (Embedded Systems Design (embedded.com)) 6/23/2010 |
| How to Make Virtual Prototyping Better than Designing with Hardware: Part 1 - Use Cases for Virtual Prototyping (Embedded Systems Design (embedded.com)) 6/22/2010 |
| Is IP Integration the Real High-Level Design? (EDN Magazine) 6/21/2010 |
| Achieving Verification Closure with Resource and Time Constraints (EDA DesignLine) 6/17/2010 |
| Altering the SOC Design Flow (EDN Magazine) 6/17/2010 |
| Challenges in Verification of Clock Domain Crossings (DAC Knowledge Center) 6/17/2010 |
| Creating Virtual Platforms Using the OCP-IP Modeling Kit (Design & Reuse) 6/17/2010 |
| Power Analysis of Clock Gating at RTL (EDA DesignLine) 6/17/2010 |
| Reducing Switching Power with Intelligent Clock Gating (Programmable Logic DesignLine) 6/17/2010 |
| Repeatable Results with Design Preservation (Programmable Logic DesignLine) 6/17/2010 |
| A Monitor-Based Approach to Verification (TechOnLine, Inc.) 6/2/2010 |
| Transitioning from C/C++ to SystemC in High-Level Design (Embedded Systems Design (embedded.com)) 6/1/2010 |
| Code Coverage Convergence In Configurable IP (Design & Reuse) 5/27/2010 |
| The "Off-the-Shelf" IPs for Today's SoCs (Embedded Systems Design (embedded.com)) 5/24/2010 |
| Continuous Integration of Complex Reconfigurable Systems (Design & Reuse) 5/20/2010 |
| Design Challenges in DRL (Programmable Logic DesignLine) 5/19/2010 |
| Implementing PCI Express Bridging Solutions In an FPGA (Embedded Computing Design) 5/19/2010 |
| Producing and Verifying Quality FPGA IP (Embedded Computing Design) 5/19/2010 |
| Protecting FPGAs from Power Analysis Attacks (Programmable Logic DesignLine) 5/18/2010 |
| Building Cost-Effective and Robust SOC-based Network Appliances (Embedded Systems Design (embedded.com)) 5/17/2010 |
| The Need for Variable Precision DSP Architecture (Programmable Logic DesignLine) 5/15/2010 |
| The Documentation Challenge (EDA DesignLine) 5/13/2010 |
| Scratching the Surface: The 2010 EDN DSP Directory (EDN Magazine) 4/22/2010 |
| Timing Closure On FPGAs (Programmable Logic DesignLine) 4/22/2010 |
| An Application-Specific Processor for Many-Core Architectures (Design & Reuse) 4/15/2010 |
| Incorporating Quality Into Reusable Interface IP (Design & Reuse) 4/15/2010 |
| Treat Programmable Hardware Design As a High-Level System Task (Embedded Systems Design (embedded.com)) 4/13/2010 |
| Soft Design and Hard Reality (Electronic Products) 4/12/2010 |
| DDR3 Memory Interface Controller IP Speeds Data-Processing Applications (Programmable Logic DesignLine) 4/6/2010 |
| Is Semiconductor Industry Consolidation Inevitable? (Electronic Engineering Times (EE Times)) 4/5/2010 |
| Setting Up Hardware Verification Testbenches Using OVM Configuration Classes (Embedded Systems Design (embedded.com)) 4/5/2010 |
| RTL Synthesis Can Accelerate the Entire Implementation Flow (EDA DesignLine) 3/31/2010 |
| A Step-By-Step Methodical Approach for Efficient Mixed-Language IP Integration (Design & Reuse) 3/22/2010 |
| Polyphase Techniques Let You Create Large Filters In Smaller Implementations In Mid-Range FPGAs (EDN Magazine) 3/18/2010 |
| Building Quality Assurance Into Your Hardware: EDA Is Not Enough! (EDA DesignLine) 3/17/2010 |
| The Evolution of FPGA Coprocessing (Electronic Products) 3/15/2010 |
| Selecting an Embedded MCU: How to Avoid the Evaluation Trap? (Design & Reuse) 3/11/2010 |
| Evolving to a Total IP Solutions to Accelerate SOC Design (Design & Reuse) 3/4/2010 |
| The Importance of FPGA-to-ASIC Solutions to Accelerate CPU-Based Protocols (Embedded Systems Design (embedded.com)) 3/3/2010 |
| Incorporating Quality Into Reusable IP (Embedded Systems Design (embedded.com)) 2/26/2010 |
| Hardware Solutions to the Challenges of Multimedia IP Functional Verification (Design & Reuse) 2/25/2010 |
| Software Architecture for IP verification in Operating System Environment (Design & Reuse) 2/25/2010 |
| Dodging Amdahl's Law with Message Passing, FPGA-Based Parallel Processing (Programmable Logic DesignLine) 2/24/2010 |
| High-Level Synthesis, Verification and Language (EDA DesignLine) 2/22/2010 |
| Leveraging FPGA and CPLD Digital Logic to Implement Analog-to-Digital Converters (Embedded Systems Design (embedded.com)) 2/18/2010 |
| Reusable VHDL IP In the Real World (Design & Reuse) 2/18/2010 |
| Static Verification: What’s Old Is New Again (SCDsource) 2/17/2010 |
| Re-Configurable Platform for Design, Verification and Implementation of SOCs (Design & Reuse) 2/11/2010 |
| Using Formal Verification for SOC Integration (SCDsource) 2/11/2010 |
| Partitioning an ASIC Design Into Multiple FPGAs (Programmable Logic DesignLine) 2/10/2010 |
| Improving Software Development and Verification Productivity Using IP-Based System Prototyping (Design & Reuse) 2/1/2010 |
| Increasing Bandwidth In Industrial Applications with FPGA Co-Processors (Programmable Logic DesignLine) 2/1/2010 |
| A Recipe for Verification IP: The Role of Methodology (Design & Reuse) 1/26/2010 |
| A Nuts and Bolts Engineering Approach to Using Open Source IP (Embedded Systems Design (embedded.com)) 1/25/2010 |
| Methodology for Rapid Development of Loosely Timed and Approximately Timed TLM Peripherals (Design & Reuse) 1/21/2010 |
| Automating the FPGA Design Debug Process (Embedded Systems Design (embedded.com)) 1/19/2010 |
| Using An FPGA to Tame the Power Beast In Consumer Handheld MPUs (Programmable Logic DesignLine) 1/13/2010 |
| Power Supply Design Considerations for Modern FPGAs (Programmable Logic DesignLine) 1/6/2010 |
| The Evolving Landscape of Digital Signal Processing (EDN Magazine) 12/3/2009 |
| FPGA Synthesis Can Be a Leverage Point In Your Design Flow (Programmable Logic DesignLine) 12/2/2009 |
| Embedded Display Control Applications Using FPGAs (FPGA and Programmable Logic Journal) 12/1/2009 |
| ESL Tools Take Center Stage As Designers Move Up (Electronic Design Magazine) 12/1/2009 |
| FPGA IP: Keeping Your Device Options Open (FPGA and Programmable Logic Journal) 12/1/2009 |
| The Best of Both Worlds: Optimizing OCP Slave Memory Behavior (EDA DesignLine) 11/19/2009 |
| High-Speed Board-Layout Challenges in FPGA/SDI Sub-Systems (Programmable Logic DesignLine) 11/18/2009 |
| SaaS and EDA: Are Designers Ready? (Electronic Engineering Times (EE Times)) 11/16/2009 |
| Use Formal, Online Communication to Deliver Design Quality Closure (Electronic Engineering Times (EE Times)) 11/16/2009 |
| Graphics Processing: When DIY Just Doesn't Make Sense (EDA DesignLine) 11/15/2009 |
| Enable Low-Power Design with FPGAs (Programmable Logic DesignLine) 10/30/2009 |
| FPGA IP: Keeping Your Device Options Open (FPGA and Programmable Logic Journal) 10/30/2009 |
| Adding Hardware Acceleration to the HVL Testbench (Design & Reuse) 10/29/2009 |
| What If the IP You Are Looking for Does Not Exist? (Design & Reuse) 10/29/2009 |
| A Set of VHDL IPs to Evaluate Performance of Netwoks-on-Chip (Design & Reuse) 10/22/2009 |
| Debugging FPGA Designs May Be Harder than You Expect (EDN Magazine) 10/22/2009 |
| FPGA-Based Rapid Prototyping of ASIC, ASSP, and SoC Designs (Programmable Logic DesignLine) 10/21/2009 |
| Use of an IP core Development Process to Achieve Time-to-Market and Quality Assurance in a Multi-Project Environment (Design & Reuse) 10/15/2009 |
| FPGA Design and Verification in Mechatronic Applications (Programmable Logic DesignLine) 10/13/2009 |
| IP Quality Lies Beyond Compliance Testing (EDN Magazine) 10/8/2009 |
| Clock Sources with Integrated Power Supply Noise Rejection Simplify Power Supply Design in FPGA-Based Systems (Programmable Logic DesignLine) 10/6/2009 |
| FPGA Device Reliability and the Sunspot Cycle (Embedded Systems Design (embedded.com)) 10/6/2009 |
| Using Tcl to Create a Virtual Component in Verilog (Embedded Systems Design (embedded.com)) 10/2/2009 |
| Don't Let Metastability Cause Problems in Your FPGA-Based Design (Programmable Logic DesignLine) 9/29/2009 |
| FPGA Architectural Power-Saving Techniques at 40nm (EDN Magazine) 9/23/2009 |
| Tool Up for the FPGA Blitz (Electronic Design Magazine) 9/22/2009 |
| Bridging the Worlds of Hardware and Software with USB-Based FPGA (ECN Magazine) 9/10/2009 |
| Why Programmability Is Now a Game Changer (Electronic Engineering Times (EE Times)) 9/10/2009 |
| How FPGAs Can Address MCUs' General-Purpose I/O Scaling Wall (Programmable Logic DesignLine) 9/9/2009 |
| Outsourcing an IC Design: Some Advice from the Trenches (EDN Magazine) 9/3/2009 |
| Improving Software Driver Development and Hardware Verification Productivity using Virtual Platforms (Design & Reuse) 8/27/2009 |
| Debugging Hardware Designs with an FPGA-Based Emulation Tool (Embedded Systems Design (embedded.com)) 8/24/2009 |
| Fast Design Productivity for Embedded Multiprocessor through Multi-FPGA Emulation (Design & Reuse) 8/20/2009 |
| Virtual Multi-Cores Simplify Real-Time System Design (Embedded Systems Design (embedded.com)) 7/27/2009 |
| Programmable Chips: Piecing Together an Analog Solution (EDN Magazine) 7/23/2009 |
| Deinterlacing with FPGAs for HDTVs (Video/Imaging DesignLine) 7/15/2009 |
| FPGA Verification in Embedded Video-Processing Systems (EDN Magazine) 7/9/2009 |
| High-Level Software for Embedded-System Design Doing Your Job? (EDN Magazine) 7/9/2009 |
| Securing SoC Platform Oriented Architectures with a Hardware Root of Trust (Embedded Systems Design (embedded.com)) 7/6/2009 |
| Debugging Hybrid FPGA Logic/Processor Designs (Electronic Products) 7/1/2009 |
| Balancing the Power Budget (Components in Electronics (CIE)) 6/30/2009 |
| Rapid Debug of Serial Buses in FPGAs (Embedded Systems Design (embedded.com)) 6/30/2009 |
| Match Multicore with Multiprogramming (Electronic Design Magazine) 6/25/2009 |
| Using IP Standards to Speed Path to Executable Specifications (SCDsource) 6/23/2009 |
| EDA Remains the Enabler of Much-Needed Innovation (Electronic Design Magazine) 6/18/2009 |
| Design Techniques for FPGA Power Optimization (DSP-FPGA) 6/15/2009 |
| Power vs. Performance: The Ultimate DSP Design Challenge (DSP-FPGA) 6/15/2009 |
| Designing Portability Into Silicon IP (EDN Magazine) 6/11/2009 |
| Troubleshooting a Transaction-Level Model (EDN Magazine) 6/11/2009 |
| FPGA the Holistic Way: Flow Integration from Concept to PCB (FPGA and Programmable Logic Journal) 6/9/2009 |
| Can MIPI and MDDI Co-Exist? (Design & Reuse) 6/8/2009 |
| Tailored SoC Building Using Reconfigurable IP Blocks (Design & Reuse) 6/8/2009 |
| From IP Re-use to Open Innovation - A New Trend in the Industry (Design & Reuse) 6/4/2009 |
| H.264/AVC HDTV Motion Compensation Soft IP (Design & Reuse) 6/4/2009 |
| Building an FPGA-Based Digital Down Converter (Embedded Systems Design (embedded.com)) 6/3/2009 |
| Making the Case for a New Approach to FPGA Debugging and Validation (DSP-FPGA) 5/15/2009 |
| Multiprocessor Debugging Challenges (DSP-FPGA) 5/15/2009 |
| The Drive to Lower Power (DSP-FPGA) 5/15/2009 |
| Need to Cut Cost, Risk, Time? Choose the Right FPGA Design Solution (FPGA and Programmable Logic Journal) 5/12/2009 |
| Estimating Power in FPGA Designs (EDN Magazine) 4/23/2009 |
| Processor Architecture Not a Factor for Low-Power Mobile Systems (DSP DesignLine) 4/20/2009 |
| Protecting Software IP: What Engineers Need to Know (Electronic Engineering Times (EE Times)) 4/20/2009 |
| Incremental Synthesis: Achieving Shorter Design Cycles without Quality Trade-Offs (FPGA and Programmable Logic Journal) 4/14/2009 |
| Building Image Format Conversion Designs for Broadcast Systems (FPGA and Programmable Logic Journal) 4/7/2009 |
| Using an Interface Wrapper Module to Simplify Implementing PCIe on FPGAs (Embedded Systems Design (embedded.com)) 4/7/2009 |
| FPGAs Reshape Embedded Design (EDN Magazine) 3/19/2009 |
| How Physical Synthesis Enables FPGA Design Productivity (FPGA and Programmable Logic Journal) 3/17/2009 |
| How to Reduce Power Consumption in CPLD Designs with Power Supply Cycling (Programmable Logic DesignLine) 3/11/2009 |
| A Synthesis and Partitioning Strategy for Effective Multi-FPGA Prototyping (FPGA and Programmable Logic Journal) 3/10/2009 |
| How to Detect Solder Joint Faults in Operating FPGAs in Real Time (Programmable Logic DesignLine) 3/4/2009 |
| Implementing DSP Functionality with FPGAs (Electronic Products) 3/1/2009 |
| How to Control Analog Output from a CPLD Using a Pulse Width Modulator (Programmable Logic DesignLine) 2/24/2009 |
| Verifying FPGA Designs: Simulate, Emulate, or Hope for the Best? (EDN Magazine) 2/19/2009 |
| Power-Aware FPGA Design: Part 1 (Programmable Logic DesignLine) 2/4/2009 |
| EDA Bashing (EDA DesignLine) 2/2/2009 |
| Take the FPGA Plunge (Electronic Design Magazine) 1/29/2009 |
| Programmable Logic Innovation Is Overdue (Programmable Logic DesignLine) 1/27/2009 |
| Identifying IP cores to Protect Your Investment (Design & Reuse) 1/26/2009 |
| Filter Banks, Part 1: Principles and Design Techniques (DSP DesignLine) 1/15/2009 |
| Using FPGAs in Reliable Automotive System Design (Automotive DesignLine) 1/15/2009 |
| How to Transform Video SerDes From a Nightmare to a Dream (Programmable Logic DesignLine) 1/14/2009 |
| Using Yesterday's Methodologies to Design Today'S Multi-FPGA Systems Is a Recipe for Disaster (Programmable Logic DesignLine) 1/7/2009 |
| IP Hardens Up Again (EDA Tech Forum) 12/31/2008 |
| License to Profit: Managing Your Software Assets Is a Pervasive Bottom Line Issue (EDA Tech Forum) 12/31/2008 |
| Verification IP: Solace for the Common Integration Nightmare? (New Tech Press) 12/24/2008 |
| Planning, Adopting and Implementing Adaptive Reuse (EDA DesignLine) 12/16/2008 |
| Ten 2009 Trends in System and Chip Design (SCDsource) 12/16/2008 |
| How to Exploit the Uniqueness of FPGA Silicon for Security Applications (Programmable Logic DesignLine) 12/10/2008 |
| Use Algorithmic Synthesis to Solve Your FPGA Prototyping and Design Issues (Electronic Design Magazine) 12/10/2008 |
| Verification Metrics: When is Enough Enough? (EDN Magazine) 12/5/2008 |
| Achieve Higher Accuracy Using Mixed-Signal FPGA Calibration (PlanetAnalog) 12/4/2008 |
| Reconfigurable Computing Prospects on the Rise (HPCwire) 12/3/2008 |
| Moving Motion-Control Technology to FPGAs (Programmable Logic DesignLine) 12/2/2008 |
| Video Encoding with Low-Cost FPGAs for Multi-Channel H.264 Surveillance (Video/Imaging DesignLine) 11/28/2008 |
| Minimizing the Pain of RTL Design Reviews (FPGA and Programmable Logic Journal) 11/25/2008 |
| Solving FPGA I/O Pin Assignment Challenges (Programmable Logic DesignLine) 11/19/2008 |
| Planning, Adopting and Implementing Adaptive Reuse (EDA DesignLine) 11/18/2008 |
| X Marks the Spot...the Intersection of Eco- and Financially-Friendly Computing (Programmable Logic DesignLine) 11/12/2008 |
| A SystemC/TLM Based Methodology for IP Development and FPGA Prototyping (EDA DesignLine) 11/3/2008 |
| Programmable Logic Use in Handsets: The Basics (Mobile Handset DesignLine) 11/2/2008 |
| Choosing the Right Processor Candidate: the 35th Annual EDN Microprocessor Directory (EDN Magazine) 10/30/2008 |
| Re-Engineering Obsolete ICs Using FPGAs (EDN Magazine) 10/13/2008 |
| Tool Integration for ESL Design (FPGA and Programmable Logic Journal) 10/7/2008 |
| Extending SPI4.2 Capabilities for Ethernet Services (EDN Magazine) 10/2/2008 |
| For Checking Software without Hardware, FPGAs Are the Answer (Electronic Design Magazine) 10/2/2008 |
| FPGA Timing Closure: The Whack-a-Mole Game (FPGA and Programmable Logic Journal) 9/30/2008 |
| How to Defend Against The Cloning of Your FPGA Designs (Programmable Logic DesignLine) 9/17/2008 |
| Selecting the Right FPGA Synthesis Tool (FPGA and Programmable Logic Journal) 9/16/2008 |
| Building a Configurable Embedded Processor (Embedded Systems Design (embedded.com)) 9/9/2008 |
| Comparing Low-Cost SerDes-Based FPGAs to ASSPs for PCI Express System Design (FPGA and Programmable Logic Journal) 9/9/2008 |
| OCP-IP Spec Provides Multicore Debug Interface (SCDsource) 9/9/2008 |
| PCI Express Bridging Options Enable FPGA-Based Configurable Computing (Programmable Logic DesignLine) 9/8/2008 |
| Rapid Prototyping for the 802.11 Era (EDA Tech Forum) 9/1/2008 |
| The Five Forces Driving the Semiconductor IP Market (Electronic Products) 9/1/2008 |
| Dev Kits Help Alleviate Those FPGA Design Woes (Electronic Design Magazine) 8/28/2008 |
| Microcontroller Design in FPGAs (Programmable Logic DesignLine) 8/20/2008 |
| How to Interface FPGAs to Microcontrollers (Programmable Logic DesignLine) 7/30/2008 |
| HDL-Design Challenges and Philosophies for Real-World ASIC Implementations (EDN Magazine) 7/24/2008 |
| Using Formal Verification for FPGA Designs (SCDsource) 7/22/2008 |
| Using Programmable Logic for Efficient and Effective DSP Design (Embedded Systems Design (embedded.com)) 7/22/2008 |
| How to Select an AES Solution (Programmable Logic DesignLine) 7/16/2008 |
| Protect Your FPGA Against Piracy (Electronic Design Magazine) 7/10/2008 |
| Where Is EDA Going Now? (EDN Magazine) 7/10/2008 |
| How to Overcome the Increasing Management Complexity of FPGA/PCB Pin Synchronization (Programmable Logic DesignLine) 7/2/2008 |
| Building an FPGA Design Repository (FPGA and Programmable Logic Journal) 7/1/2008 |
| Selecting and Integrating Mixed-Signal IP (SCDsource) 6/17/2008 |
| Achieving First-time Success at 40nm (EDN Magazine) 6/12/2008 |
| EDA Sales Shouldn't Be Like Buying a Used Car (SCDsource) 6/10/2008 |
| Employing an I/O Interlocutor (FPGA and Programmable Logic Journal) 6/10/2008 |
| Xilinx Speeds HDL Simulation with SecureIP and FAST Simulation Mode Models (FPGA and Programmable Logic Journal) 6/10/2008 |
| New FPGA Meets Handheld Price, Power, and Space Requirements (Programmable Logic DesignLine) 6/2/2008 |
| Implementing an Intelligent Solar Tracking Control System on an FPGA (EDA Tech Forum) 6/1/2008 |
| Avoid FPGA Project Delays by Adopting Advanced Design Methodologies (FPGA and Programmable Logic Journal) 5/27/2008 |
| FPGA Design Requires Low-Power Techniques (SCDsource) 5/6/2008 |
| How to Raise the RTL Abstraction Level and Design Conciseness with SystemVerilog: Part 1 (Programmable Logic DesignLine) 4/30/2008 |
| How to Implement SystemVerilog for FPGA Design (FPGA and Programmable Logic Journal) 4/29/2008 |
| Reconfigurable Computing: Custom Supercomputers on Demand? (Programmable Logic DesignLine) 4/15/2008 |
| Optimizing Embedded Designs (Electronic Products) 4/14/2008 |
| Specifying Transceivers for Serial Protocols (Electronic Products) 4/14/2008 |
| Reducing Power in Embedded Systems by Adding Hardware Accelerators (Embedded Systems Design (embedded.com)) 4/9/2008 |
| Implement a Complete ARV Controller in a Single SOC (Electronic Design Magazine) 3/27/2008 |
| Comparing Power Consumption of FPGAs with Customizable Microcontrollers (FPGA and Programmable Logic Journal) 3/18/2008 |
| Multimode Sensor Processing Using Massively Parallel Processor Arrays (Programmable Logic DesignLine) 3/18/2008 |
| Evolving Passive Optical Networks Demand FPGA Design Flexibility (Programmable Logic DesignLine) 3/12/2008 |
| FPGA-Based Prototyping Grows Up (Electronic Engineering Times (EE Times)) 3/10/2008 |
| Using FPGAs to Avoid Microprocessor Obsolescence (Programmable Logic DesignLine) 3/5/2008 |
| Reconfigurable Computing for Acceleration in High-performance Computing (FPGA and Programmable Logic Journal) 2/26/2008 |
| Analog's Answer to FPGA Opens Field to Masses (Electronic Engineering Times (EE Times)) 2/21/2008 |
| Comparing IP Integration Approaches for FPGA Implementation (Programmable Logic DesignLine) 2/20/2008 |
| SystemVerilog is Coming to FPGA Design (FPGA and Programmable Logic Journal) 2/19/2008 |
| How to Select a DDR Memory Controller (SCDsource) 2/13/2008 |
| Effectively Using Internal Logic Analyzers for Debugging FPGAs (FPGA and Programmable Logic Journal) 2/12/2008 |
| FPGA-Based Prototyping: "Productivity to Burn" (Programmable Logic DesignLine) 1/30/2008 |
| How to Achieve Timing-Closure in High-End FPGAs (Programmable Logic DesignLine) 1/23/2008 |
| Three "I"s of FPGA Design: Iterations, Incremental and Intelligent Design Tools (FPGA and Programmable Logic Journal) 1/22/2008 |
| New Approach to FPGA Physical Synthesis for Ease-of-Use and Wide Device Support (FPGA and Programmable Logic Journal) 1/18/2008 |
| Using FPGAs for HDTV Design (EDN Magazine) 1/17/2008 |
| USB Host IP-Core Hardware and Software Concurrent Development (Design & Reuse) 1/10/2008 |
| OCP VIP: A Cost-Effective and Robust Qualification Process for Multimedia and Telecom SOC Designs (Embedded Systems Design (embedded.com)) 1/9/2008 |
| The Art of FPGA Construction (Embedded Systems Design (embedded.com)) 1/6/2008 |
| Dealing with the Challenges of Integrating Hardware and Software Verification (Embedded Systems Design (embedded.com)) 1/4/2008 |
| Wavelet Data Hiding Using Achterbahn-128 on FPGAs (Programmable Logic DesignLine) 12/26/2007 |
| Quantify FPGA System-Level Simultaneous Switching Noise in a Chip/ Package/ PCB Design (Embedded Systems Design (embedded.com)) 12/21/2007 |
| Lower the Cost of Intelligent Power Control with FPGAs (Embedded Systems Design (embedded.com)) 12/15/2007 |
| Using Off-the-Shelf Technology with an FPGA to Replace Custom Hardware: Picking platforms, Tools (Industrial Control DesignLine) 12/14/2007 |
| Zero-Power CPLDs Enable Low-Power Portable Applications (Mobile Handset DesignLine) 12/13/2007 |
| Applying FPGAs in System-Critical Automotive Electronics (Automotive DesignLine) 12/12/2007 |
| Designing DDR3 SDRAM Controllers with Today's FPGAs (Programmable Logic DesignLine) 12/12/2007 |
| Using CPLDs to Replace or Augment Microcontrollers (FPGA and Programmable Logic Journal) 12/11/2007 |
| Choosing the Right Industrial Control and Acquisition Hardware: FPGAs vs. PLCs vs. Custom Hardware (Industrial Control DesignLine) 12/7/2007 |
| Convert an FPGA to a Gate Array at Project Start (Electronic Engineering Times (EE Times)) 12/7/2007 |
| Virtually Every ASIC Ends Up an FPGA (Electronic Engineering Times (EE Times)) 12/7/2007 |
| Ethernet and Multimedia Applications: Part 2 (Programmable Logic DesignLine) 11/28/2007 |
| Improving ADC Results Through Oversampling and Post-Processing of Data (FPGA and Programmable Logic Journal) 11/27/2007 |
| Ethernet and Multimedia Applications: Part 1 (Programmable Logic DesignLine) 11/21/2007 |
| Physical Synthesis Flows for FPGA Designs (FPGA and Programmable Logic Journal) 11/20/2007 |
| A –48V Hot-Swap Controller Design Targets High-Power Blades (EDN Magazine) 11/19/2007 |
| FPGA Processors Take New Directions (SCDsource) 11/15/2007 |
| FPGAs Control Graphics and Video in Embedded Systems (FPGA and Programmable Logic Journal) 11/13/2007 |
| Interfacing FPGAs to DDR3 SDRAM memories (EDN Magazine) 11/8/2007 |
| High Noon for FPGAs: Low-cost vs. high-end Showdown (EDN Magazine) 11/5/2007 |
| OpenAccess Expands to New Horizons (SCDsource) 11/5/2007 |
| Duct Tape, FPGAs, and the Art of Making Great Multi-Purpose Tools (FPGA and Programmable Logic Journal) 10/30/2007 |
| FPGA-Based Hardware Acceleration of C/C++ Based Applications: Part 4 (Programmable Logic DesignLine) 10/24/2007 |
| FPGA-Based Access Flow Processors (AFPs) for DSLAM Line Cards (Programmable Logic DesignLine) 10/17/2007 |
| Customer-Specific Product Platforms Speed Mobile Devices Designs, Reduce BOM (Wireless Net DesignLine) 10/16/2007 |
| Low-Power Portable Product Design with FPGAs (Programmable Logic DesignLine) 10/10/2007 |
| FPGA-Prototyping and ASIC-Conversion Considerations (EDN Magazine) 10/3/2007 |
| How to Implement Double-Precision Floating-Point on FPGAs (Programmable Logic DesignLine) 10/3/2007 |
| Using FPGAs for Advanced Collision Avoidance Systems (Embedded Systems Design (embedded.com)) 10/3/2007 |
| Cost-Effective Two-Dimensional Rank-Order Filters on FPGAs (DSP DesignLine) 9/20/2007 |
| Multimedia Signal Processing with Programmable Logic (Video/Imaging DesignLine) 9/14/2007 |
| How to Enhance Signal Integrity in High-Density FPGA-based Designs (Embedded Systems Design (embedded.com)) 9/13/2007 |
| How to Use FPGAs for Quadrature Encoder-based Motor Control Applications (Programmable Logic DesignLine) 9/11/2007 |
| Top-down DSP Design for FPGAs (Programmable Logic DesignLine) 9/5/2007 |
| Regression Test for OCP SystemC Channel Models (EDA DesignLine) 9/4/2007 |
| FPGA-based Design Yields Low-Cost Arbitrary-Frequency Generator (EDN Magazine) 9/3/2007 |
| How to Support Multiple SD Devices Using CPLDs (Programmable Logic DesignLine) 8/22/2007 |
| Design Tool Evolution (FPGA and Programmable Logic Journal) 8/21/2007 |
| Embedded Developers Should Embrace FPGAs (EDA DesignLine) 8/9/2007 |
| FPGA-based Hardware Acceleration of C/C++ Based Applications: Part 2 (Programmable Logic DesignLine) 8/1/2007 |
| Using Memory Analysis to Create Leaner, Faster, More Reliable Embedded Systems (DSP-FPGA.com) 8/1/2007 |
| FPGA vs. DSP Design Reliability and Maintenance (DSP-FPGA.com) 7/25/2007 |
| FPGA-Based Hardware Acceleration of C/C++ Based Applications: Part 1 (Programmable Logic DesignLine) 7/25/2007 |
| Is FPGA a Simpler Puzzle for ASIC Designers? (EDN Magazine) 7/19/2007 |
| How to Implement a Compact, Cost-Effective, and Low-Power Ethernet-to-Network Processor Bridge (Programmable Logic DesignLine) 7/11/2007 |
| FPGAs and Ethernet: Providing Programmability to a Pervasive Interconnect Standard (FPGA and Programmable Logic Journal) 7/10/2007 |
| Software-Intensive ASICs/ASSPs Demand Integrated Prototyping Solutions (EDA DesignLine) 6/22/2007 |
| How Customer-Specific Standard Products Ease Mobile Device Design (Programmable Logic DesignLine) 6/20/2007 |
| The Incredible Journey of an 800-ps Period (Programmable Logic DesignLine) 6/13/2007 |
| Using FPGAs to Interface with Digital Communication Protocols (Programmable Logic DesignLine) 6/6/2007 |
| FPGA Packaging and Signal Integrity: A Connectivity Perspective (FPGA and Programmable Logic Journal) 5/29/2007 |
| How to Simplify Hardware Prototyping with EXP Modules (Programmable Logic DesignLine) 5/23/2007 |
| How to Choose an RTOS for Your FPGA and ASIC Designs (Programmable Logic DesignLine) 5/9/2007 |
| The Value of a Complete FPGA Design Flow (FPGA and Programmable Logic Journal) 5/1/2007 |
| How to Build Ultra-Fast Floating-Point FFTs in FPGAs (DSP DesignLine) 4/30/2007 |
| HD-Video Encoding with DSP and FPGA Partitioning (EDN Magazine) 4/26/2007 |
| A Tutorial on Tools, Techniques, and Methodology to Improve FPGA Designer Productivity (Programmable Logic DesignLine) 4/25/2007 |
| How to Test the Interconnections Between FPGAs on a High-Density FPGA-based Board (Programmable Logic DesignLine) 4/11/2007 |
| Next-Generation 65-nm FPGAs (FPGA and Programmable Logic Journal) 4/10/2007 |
| Designing PC Boards with Speedy FPGAs (Embedded Systems Design (embedded.com)) 4/9/2007 |
| Expanding Applications for Low-cost FPGAs (Programmable Logic DesignLine) 4/4/2007 |
| Challenge the Assumptions on FPGAs (DSP DesignLine) 4/2/2007 |
| Migrating FPGAs to Structured ASICs in Avionics to Reduce SEU Susceptibility (DSP-FPGA.com) 4/1/2007 |
| How to Simplify the Process of Specifying Register-Maps and Auto-Generating Code and Other Deliverables (Programmable Logic DesignLine) 3/28/2007 |
| Putting FPGAs to Work in Software Radio Systems: Part 3 (Microwave & RF DesignLine) 3/28/2007 |
| Putting FPGAs to Work in Software Radio Systems: Part 2 (Microwave & RF DesignLine) 3/21/2007 |
| FPGA Design Issues 201 (Electronic Design Magazine) 3/15/2007 |
| How FPGAs can tackle the challenges of network security (Programmable Logic DesignLine) 3/14/2007 |
| Putting FPGAs to Work in Software Radio Systems: Part 1 (Microwave & RF DesignLine) 3/14/2007 |
| Deterministic Name Generation for Incremental Synthesis (FPGA and Programmable Logic Journal) 3/13/2007 |
| Design Preservation with SmartCompile and Xilinx Design Tools (Programmable Logic DesignLine) 3/7/2007 |
| A New Architecture for Development Platforms Targeted to Portable Radio Applications (DSP-FPGA.com) 2/28/2007 |
| How to Improve Design-Level Security with Low-Cost Non-Volatile FPGAs (Programmable Logic DesignLine) 2/28/2007 |
| Reprogrammable Logic Drives Automotive Vision Systems Design (FPGA and Programmable Logic Journal) 2/27/2007 |
| How to Use M and Simulink for DSP Control and Datapath Design (Programmable Logic DesignLine) 2/21/2007 |
| FPGA I/O Design Is (also) a PCB Problem (FPGA and Programmable Logic Journal) 2/20/2007 |
| How to Design an FPGA Architecture Tailored for Efficiency and Performance (Programmable Logic DesignLine) 2/12/2007 |
| Achieving Timing Convergence (EDA DesignLine) 2/8/2007 |
| Generate FPGA Accelerators from C (DSP DesignLine) 2/8/2007 |
| Getting the Most Out of ASIC Prototyping with FPGAs (Programmable Logic DesignLine) 2/7/2007 |
| Getting the Most Out of ASIC Prototyping with FPGAs (Programmable Logic DesignLine) 2/7/2007 |
| Reducing FPGA Compile Time Using Parallel Compilation Methodology (EDA DesignLine) 2/5/2007 |
| Designing Custom Embedded Multicore Processors (Embedded Systems Design (embedded.com)) 2/1/2007 |
| Evaluating IP with the Four Cs: Compare, Consider, Collect, and Calculate (EDN Magazine) 2/1/2007 |
| Programmable Accelerators: Hardware Performance with Software Flexibility (DSP DesignLine) 2/1/2007 |
| How to Design 65-nm FPGA DDR2 Memory Interfaces for Signal Integrity (Programmable Logic DesignLine) 1/24/2007 |
| How to Achieve Software Load-Balance by Using a Message-Based Interconnect Protocol (Programmable Logic DesignLine) 1/22/2007 |
| How to Choose the Right FPGA (DSP DesignLine) 1/18/2007 |
| How to Achieve Faster Compile Times in High-Density FPGAs (Programmable Logic DesignLine) 1/17/2007 |
| How to Maximize FPGA Performance (Programmable Logic DesignLine) 1/15/2007 |
| FPGA Floating Point Performance: A Pencil and Paper Evaluation (HPCwire) 1/12/2007 |
| Video and Image Processing Design Using FPGAs (Video/Imaging DesignLine) 1/12/2007 |
| FPGAs vs. DSPs: A Look at the Unanswered Questions (DSP DesignLine) 1/11/2007 |
| Achieving 100% Visibility with FPGA-based ASIC Prototypes Running at Real-Time Hardware Speeds (Programmable Logic DesignLine) 1/8/2007 |
| Power Exploration in High-Level Synthesis (FPGA and Programmable Logic Journal) 12/19/2006 |
| Floating-point Arithmetic on FPGAs (DSP DesignLine) 12/13/2006 |
| System Management: Not Sexy, but Critical (FPGA and Programmable Logic Journal) 12/12/2006 |
| Unified FPGA-ASIC Design Flow Provides Designers Versatility in Meeting Production Goals (FPGA and Programmable Logic Journal) 12/5/2006 |
| How to Implement High-Security in Low-Cost FPGAs (Programmable Logic DesignLine) 12/4/2006 |
| How to Use CPLDs to Implement a QWERTY Keypad (Programmable Logic DesignLine) 11/30/2006 |
| Focus on FPGA Programmable Platform for Industrial Systems (Industrial Control DesignLine) 11/29/2006 |
| Speed Hardware Development with Model-Based Design (DSP DesignLine) 11/24/2006 |
| Low-cost Kits: The New FPGA-Designer Trend (EDN Magazine) 11/23/2006 |
| How to Use Programmable Analog for High-Power LED Color Mixing Applications (Programmable Logic DesignLine) 11/15/2006 |
| Computational Bottlenecks and Hardware Decisions for FPGAs (FPGA and Programmable Logic Journal) 11/14/2006 |
| Speed Up Downconverter Implementation with Rapid Prototyping (Wireless Net DesignLine) 11/13/2006 |
| How to Get More Performance in 65-nm FPGA Designs (Programmable Logic DesignLine) 11/7/2006 |
| Low-Cost ASIC Conversion Targets Consumer Success (FPGA and Programmable Logic Journal) 11/7/2006 |
| How to Utilize Advanced FPGA Features without Getting Locked into an Architecture (Programmable Logic DesignLine) 10/18/2006 |
| How to Design FPGA-based Advanced PCI Express Endpoint Solutions (Programmable Logic DesignLine) 10/16/2006 |
| Designing Dual-Modulus Dividers in an FPGA (EDN Magazine) 9/28/2006 |
| How to Use CPLDs to Manage Average Power Consumption in Portable Applications (Programmable Logic DesignLine) 9/26/2006 |
| How to Reduce Power Using I/O Gating (CPLDs) versus Sleep Modes (FPGAs) (Programmable Logic DesignLine) 9/20/2006 |
| Analyze DSP Designs in FPGAs with the Z-Transform (DSP DesignLine) 9/18/2006 |
| How to Get the Best Cost Savings When Implementing an FPGA-to-ASIC Conversion (Programmable Logic DesignLine) 9/6/2006 |
| Bit-Based Dynamic Alignment for Multi-Gigabit Parallel I/O (FPGA and Programmable Logic Journal) 8/29/2006 |
| Integrating PCB and FPGA Constraints (FPGA and Programmable Logic Journal) 8/22/2006 |
| The "Nuts and Bolts" of Integrating PCI Express Into Your Design (Programmable Logic DesignLine) 8/2/2006 |
| SIC of Figuring Out the Best ASIC Solution? (Electronic Design Magazine) 7/20/2006 |
| Core-Aassisted Approach Accelerates Debug of FPGA DDR II Interfaces (Programmable Logic DesignLine) 6/21/2006 |
| FPGAs Balance Lower Power, Smaller Nodes Drip by Drip (EDN Magazine) 6/8/2006 |
| Implementing PCI Express Designs Using FPGAs (Programmable Logic DesignLine) 6/7/2006 |
| Should You Reuse RTL? (FPGA and Programmable Logic Journal) 6/6/2006 |
| On the Cutting-Edge of FPGA Design and Verification (FPGA and Programmable Logic Journal) 5/16/2006 |
| How Hybrid Structured ASICs Provide Low-Cost Solutions for Mid-Range Applications (Programmable Logic DesignLine) 5/10/2006 |
| A Low-Cost Solution for FPGA-Based PCI Express Implementation (Programmable Logic DesignLine) 5/3/2006 |
| Keys to Simulation Acceleration and Emulation Success (EDN Magazine) 4/27/2006 |
| How to lower the cost of PCI Express adoption by using FPGAs (Programmable Logic DesignLine) 4/26/2006 |
| Combining FPGAs and DSPs to Get the Best Performance (Wireless Net DesignLine) 4/18/2006 |
| Using Complex Triggers in an FPGA-Based RTL Debugger (Programmable Logic DesignLine) 4/12/2006 |
| FPGA Partial Reconfiguration Mitigates Variability (eeDesign (EE Times EDA News)) 4/3/2006 |
| FPGAs for Prototyping; ASICs for Production (Programmable Logic DesignLine) 3/28/2006 |
| All About FPGAs (Programmable Logic DesignLine) 3/21/2006 |
| Are You Designing with Too Many Significant Figures? (FPGA and Programmable Logic Journal) 3/21/2006 |
| FPGAs Poised to Play in Embedded Applications (DSP-FPGA.com) 3/17/2006 |
| Image Processing Applications on New Generation FPGAs (FPGA and Programmable Logic Journal) 3/7/2006 |
| Increasing Visibility in FPGA Prototypes and Emulators (Programmable Logic DesignLine) 3/7/2006 |
| How to Achieve Fast Timing Closure on FPGA Designs (Programmable Logic DesignLine) 3/1/2006 |
| Think You Know Where Structured ASICs Belong? (FPGA and Programmable Logic Journal) 2/28/2006 |
| How to Avoid PCB Libraries Stifling FPGA Design (FPGA and Programmable Logic Journal) 2/21/2006 |
| Spring "Board" To FPGA Design Success (Electronic Design Magazine) 2/16/2006 |
| Reconfigurable Computing in Real-World Applications (FPGA and Programmable Logic Journal) 2/7/2006 |
| Compiling FPGA Netlists for Formal Verification (eeDesign (EE Times EDA News)) 2/6/2006 |
| Choosing Hardware IP (Embedded Systems Design (embedded.com)) 2/1/2006 |
| Taming Embedded Multi-Core on FPGAs for Packet Processing (FPGA and Programmable Logic Journal) 1/31/2006 |
| Optimizing DSP Functions in Advanced FPGA Architectures (Programmable Logic DesignLine) 1/25/2006 |
| Program Flash Memory Using Parallel Flash Loaders and CPLDs (Embedded Systems Design (embedded.com)) 1/24/2006 |
| Choose the Right Mix of Processing Technologies for Embedded-System Designs (EDN Magazine) 1/19/2006 |
| Meeting Signal Integrity Requirements in FPGAs with High-End Memory Interfaces (Programmable Logic DesignLine) 1/18/2006 |
| A Practical Approach to Reusing HDL Code in FPGA Designs (Programmable Logic DesignLine) 12/28/2005 |
| Just What Is Algorithmic Synthesis? (FPGA and Programmable Logic Journal) 12/6/2005 |
| Network Require Multi-Gigabit Processing? Try Multi-Core FPGAs (Network Systems Designline) 12/5/2005 |
| How to Reduce Costs by Integrating PCI Interface Functions into CPLDs (Programmable Logic DesignLine) 11/30/2005 |
| Need More Performance? Simply Increasing the Clock Frequency May Not be the Answer (FPGA and Programmable Logic Journal) 11/29/2005 |
| Power Considerations in Designing with 90m FPGAs (Programmable Logic DesignLine) 11/23/2005 |
| The Case for Hardware/Software Co-Verification (FPGA and Programmable Logic Journal) 11/8/2005 |
| Building an FPGA FIFO without Using Logic Resources (Programmable Logic DesignLine) 11/7/2005 |
| Dual-Port FPGA Memory Blocks: The Ultimate System Interconnect Solution?
(Programmable Logic DesignLine) 11/2/2005 |
| Routing Density Analysis of ASICs, Structured ASICs, and FPGAs (Programmable Logic DesignLine) 10/19/2005 |
| Best Practices for Structured-ASIC Design (Electronic Engineering Times (EE Times)) 10/17/2005 |
| Carefully Weigh the Tradeoffs of Cell-Based vs. Structured ASICs (Electronic Design Magazine) 10/13/2005 |
| FPGA Soft Processor Design Considerations (Programmable Logic DesignLine) 10/12/2005 |
| Architectural-Design Considerations for Implementing Hardware Acceleration (EDN Magazine) 9/29/2005 |
| Making the Case for Live at Power-Up (Programmable Logic DesignLine) 9/21/2005 |
| It’s Not All About the FPGA Anymore (FPGA and Programmable Logic Journal) 9/15/2005 |
| One Design Fits All (EDN Magazine) 9/15/2005 |
| How to Save Costs Using Mature Process Technologies (Programmable Logic DesignLine) 9/12/2005 |
| FPGA Reliability in Space-Flight and Automotive Applications (FPGA and Programmable Logic Journal) 9/6/2005 |
| Migrating FPGA Virtual Gates to MROM Reduces Reliability Risk (FPGA and Programmable Logic Journal) 9/6/2005 |
| Low-Cost FPGAs: The ASIC Alternative (Electronic Design Magazine) 9/1/2005 |
| Closely Coupled Co-processors for Algorithmic Acceleration (FPGA and Programmable Logic Journal) 8/30/2005 |
| PCI Express Design Considerations: Platform ASIC vs. FPGA Design Efficiency (FPGA and Programmable Logic Journal) 8/23/2005 |
| Algorithmic C Synthesis Fuels Functional Reuse (FPGA and Programmable Logic Journal) 8/9/2005 |
| Optimizing Programmable Devices for Bus Interfaces, Bridges and Control (FPGA and Programmable Logic Journal) 8/2/2005 |
| Good Engineering Practices Minimize Design-Porting Effort (Chip Design Magazine) 8/1/2005 |
| A New Spin on FPGA Re-Spins (FPGA and Programmable Logic Journal) 7/12/2005 |
| Structured ASICs Deserve Serious Attention at 90 nm (EDN Magazine) 7/7/2005 |
| What the Hell is ESL? (FPGA and Programmable Logic Journal) 6/21/2005 |
| Are These Guys Dense, or What? Newest Class of FPGAs Makes Dense Cool (FPGA and Programmable Logic Journal) 6/14/2005 |
| FPGAs Enabling Consumer Electronics: A Growing Trend (FPGA and Programmable Logic Journal) 6/14/2005 |
| Accelerating C Software Applications Using a CompactFlash FPGA Accelerator Card (FPGA and Programmable Logic Journal) 6/7/2005 |
| Advantages Abound for a Conversion-Free, Low-Cost Path to Volume Production (Chip Design Magazine) 6/1/2005 |
| Navigating the Silicon Jungle: FPGA or ASIC? (Chip Design Magazine) 6/1/2005 |
| Core Sample: IP for Increased Productivity (FPGA and Programmable Logic Journal) 5/31/2005 |
| Redefining Structured ASIC (FPGA and Programmable Logic Journal) 5/30/2005 |
| Selecting the FPGA that Meets Your Signal Integrity Requirements (FPGA and Programmable Logic Journal) 5/17/2005 |
| The Programmable Base Station (FPGA and Programmable Logic Journal) 5/3/2005 |
| Power: Suddenly, We Care (FPGA and Programmable Logic Journal) 4/28/2005 |
| Clock Watching: Unraveling Complex Clocking (FPGA and Programmable Logic Journal) 3/29/2005 |
| Free Tool Friday: How Good Are FPGA Vendor Tools? (FPGA and Programmable Logic Journal) 3/22/2005 |
| A Methodology for DSP-Based FPGA Design (eeDesign (EE Times EDA News)) 3/9/2005 |
| Plug and Play Design Methodologies for FPGA-based Signal Processing (FPGA and Programmable Logic Journal) 3/8/2005 |
| Design FPGA-Based DSPs for Performance and Power (Chip Design Magazine) 3/1/2005 |
| Coverification Methodology for Platform FPGAs (FPGA and Programmable Logic Journal) 2/22/2005 |
| Making the Jump to 10G (FPGA and Programmable Logic Journal) 2/22/2005 |
| How to Create Beam-Forming Smart Antennas Using FPGAs (Embedded Systems Design (embedded.com)) 2/17/2005 |
| Simulator Savvy: Getting the Most from Your HDL (FPGA and Programmable Logic Journal) 2/15/2005 |
| The Impact of Timing Exceptions on FPGA Performance (FPGA and Programmable Logic Journal) 2/15/2005 |
| FPGA-based System-on-Module Approach Cuts Time to Market, Avoids Obsolescence (FPGA and Programmable Logic Journal) 2/8/2005 |
| Prime-time Processing: Are Embedded Systems on FPGA Ready? (FPGA and Programmable Logic Journal) 2/8/2005 |
| Sorting Data in Two Clock Cycles (Embedded Systems Design (embedded.com)) 1/27/2005 |
| Considering the Total Cost of FPGAs (FPGA and Programmable Logic Journal) 1/25/2005 |
| Structured ASIC Starting Line (FPGA and Programmable Logic Journal) 1/25/2005 |
| Accelerating Processor-based Systems (FPGA and Programmable Logic Journal) 1/18/2005 |
| Debug Dilemma: Simulate or Emulate? (FPGA and Programmable Logic Journal) 1/11/2005 |
| Deliver Products On-Time with RTL Hardware Debug (FPGA and Programmable Logic Journal) 1/11/2005 |
| FPGAs Supplant Processors and ASICs In Advanced Imaging Applications (FPGA and Programmable Logic Journal) 1/4/2005 |
| New FPGA Products Hit the Streets (FPGA and Programmable Logic Journal) 1/4/2005 |
Tutorials, White Papers & Conference Papers on FPGAs/CPLDs/PLDs (back to top) |
| A Complete Design Solution for Structured ASICs (Magma Design Automation, Inc.) |
| A Fast Hardware/Software Co-Verification Method for System-on-a-Chip by Using a C/C++ Simulator and FPGA Emulator with Shared Register Communication (Design Automation Conference (DAC)) |
| A Fast HW/SW FPGA-Based Thermal Emulation Framework for Multi-Processor System-on-Chip (Design Automation Conference (DAC)) |
| A Flexible Architecture to Drive Sharp Two-Way Viewing Angle and Standard LCDs (Altera Corp.) |
| A Guide to Using FPGAs for Application-Specific Digital Signal Processing (Xilinx, Inc.) |
| A Hardware-Software Partitioning and Scheduling Algorithm for Dynamically Reconfigurable Embedded Systems (IMEC) |
| A High Performance Encryption Core for Wireless 3G Networks (Design Automation Conference (DAC)) |
| A Method to Decompose Multiple-Output Logic Functions (Design Automation Conference (DAC)) |
| A New Hybrid FPGA With Nanoscale Clusters and CMOS Routing (Design Automation Conference (DAC)) |
| A Survival Guide for Selecting High-Quality IP (Synopsys, Inc.) |
| Accelerating System-on-Chip Power Analysis Using Hybrid Power Estimation (47.4) (Design Automation Conference (DAC)) |
| Accelerating WiMAX System Design with FPGAs (Altera Corp.) |
| Achieving Design Closure with Constraint-Driven Synthesis (Mentor Graphics Corp.) |
| Achieving Low Power in 65-nm Cyclone III FPGAs (Altera Corp.) |
| An Adaptive FPGA Architecture with Process Variation Compensation and Reduced Leakage (Design Automation Conference (DAC)) |
| An Algorithm for Converting Floating-Point Computations to Fixed-Point in MATLAB Based FPGA Design (Design Automation Conference (DAC)) |
| An Approach to Placement-Coupled Logic Replication (Design Automation Conference (DAC)) |
| An Area Estimation Methodology for FPGA Based Designs at SystemC-Level (Design Automation Conference (DAC)) |
| An Efficient Algorithm for Finding Empty Space for Online FPGA Placement (Design Automation Conference (DAC)) |
| An High-End Realtime Stream Processing Library for FPGAs (49.2) (Design Automation Conference (DAC)) |
| An Introduction to Home Networking (Xilinx, Inc.) |
| An SoC Design Methodology Using FPGA and Embedded Microprocessors (Design Automation Conference (DAC)) |
| Architecture-Adaptive Range Limit Windowing for Simulated Annealing FPGA Placement (Design Automation Conference (DAC)) |
| Architecture-Aware FPGA Placement Using Metric Embedding (30.1) (Design Automation Conference (DAC)) |
| Area Constraint Evaluation for FPGAs (Synplicity, Inc.) |
| Area-Efficient Instruction Set Synthesis for Reconfigurable System-on-Chip Designs (Design Automation Conference (DAC)) |
| ASIC Verification in Transition: How to Get the Most Out of FPGA Prototyping! (Synplicity, Inc.) |
| Automatic Generation of Customized Discrete Fourier Transform (Design Automation Conference (DAC)) |
| Automatic Translation of Software Binaries onto FPGAs (Design Automation Conference (DAC)) |
| Benefits and Applications of the Wireless USB WHCI Host and Dual-Role Device (Synopsys, Inc.) |
| Benefits and Challenges of Platform Based Design (Design Automation Conference (DAC)) |
| Block-Based Prototyping (Aptix Corp.) |
| Boundary Scan Tutorial (Corelis, Inc.) |
| Broadcast Video Infrastructure Implementation Using FPGAs (Altera Corp.) |
| Building a Total Quality Experience into Silicon IP: Delivering DesignWare Silicon IP into SoC Designs (Synopsys, Inc.) |
| Combining Impulse C with uClinux for MicroBlaze-based FPGAs (Impulse Accelerated Technologies, Inc.) |
| Concurrent FPGA-PCB Design within an Integrated Design Environment (Aldec, Inc.) |
| DDBDD: Delay-Driven BDD Synthesis for FPGAs (49.1) (Design Automation Conference (DAC)) |
| Delivering Synthesizable Verification IP for Test Benches (Bluespec, Inc.) |
| Design Space Exploration and Prototyping for On-Chip Multimedia Applications (Design Automation Conference (DAC)) |
| Designing Flexible Fast CAMs with Virtex Family FPGAs (Xilinx, Inc.) |
| Designing State Machines for FPGAs (Actel Corp.) |
| Develop or Buy Verification IP? (nSys Design Systems Pvt. Ltd.) |
| Device and Architecture Co-Optimization for FPGA Power Reduction (Design Automation Conference (DAC)) |
| DSP Co-Processing in FPGAs: Embedding High-Performance, Low-Cost DSP Functions (Xilinx, Inc.) |
| Dynamic FPGA Routing for Just-in-Time FPGA Compilation (Design Automation Conference (DAC)) |
| Efficient On-Line Testing of FPGAs with Provable Diagnosabilities (Design Automation Conference (DAC)) |
| Efficient SAT-based Boolean Matching for FPGA Technology Mapping (Design Automation Conference (DAC)) |
| Efficient Static Buffering to Guarantee Throughput-Optimal FPGA Implementation of Synchronous Dataflow Graphs (University of Maryland (ECE)) |
| Electronics: The New Differential in the Automotive Industry (26.1) (Design Automation Conference (DAC)) |
| Emulation: Enabling It on Every Desktop (Bluespec, Inc.) |
| Enabling Assertion-Based Verification (Zocalo Tech, Inc.) |
| Enhancing FPGA Performance for Arithmetic Circuits (18.4) (Design Automation Conference (DAC)) |
| Estimating FPGA Requirements for DSP Applications (Hunt Engineering, Ltd.) |
| Estimating Performance and Capacity of Actel Devices (Actel Corp.) |
| Examining ARM's Cortex Microcontroller Software Interface Standard (Feabhas, Ltd.) |
| Exploring Regular Fabrics to Optimize the Performance-Cost Trade-Off (eASIC Corp.) |
| Exploring Technology Alternatives for Nano-Scale FPGA Interconnects (Design Automation Conference (DAC)) |
| Fast, Efficient RTL Debug for Programmable Logic Designs (Synplicity, Inc.) |
| Favorable Economics Will Drive Rapid Adoption of Certified Wireless USB (Synopsys, Inc.) |
| FLAW: FPGA Lifetime AWareness (Design Automation Conference (DAC)) |
| Flexible ASIC: Shared Masking for Multiple Media Processors (Design Automation Conference (DAC)) |
| FPGA Architectures Overview (1-CORE Technologies) |
| FPGA Design Tutorial (1-CORE Technologies) |
| FPGA Enabled Home Networking Technology Bridges: Connecting Disparate Technologies (Xilinx, Inc.) |
| FPGA Logic Cells Comparison (1-CORE Technologies) |
| FPGA Performance Benchmarking Methodology (Altera Corp.) |
| FPGA Power Reduction Using Configurable Dual-Vdd (Design Automation Conference (DAC)) |
| FPGA Synthesis: The Vendor-Independent Approach (Mentor Graphics Corp.) |
| FPGA Technology Mapping: A Study of Optimality (Design Automation Conference (DAC)) |
| FPGA vs. DSP Design Reliability and Maintenance (Altera Corp.) |
| FPGA-Based Design and Implementation of the 3GPP-LTE Physical Layer Using Parameterized Synchronous Dataflow Techniques (University of Maryland (ECE)) |
| FPGA-based Prototyping: Why All ASICs Should be Prototyped Using FPGAs (Synplicity, Inc.) |
| FPGAs for High-Performance DSP Applications (Altera Corp.) |
| FPGAs for Software Radio (Pentek, Inc.) |
| FPGAs Provide Reconfigurable DSP Solutions (Altera Corp.) |
| FPGAs Tackle DSP Applications for Communications (Pentek, Inc.) |
| FPGAs: Fast Track to DSP (Mentor Graphics Corp.) |
| FPGAs: Under the Hood (National Instruments Corp.) |
| Getting Started with Xilinx FPGAs Video Guide (BurchED) |
| GlitchMap: An FPGA Technology Mapper for Low Power Considering Glitches (18.1) (Design Automation Conference (DAC)) |
| HDL Methodology Offers Fast Design Cycle and Vendor Independence (Actel Corp.) |
| Hi-Fi Audio: Unveiling the Hidden dBs (Synopsys, Inc.) |
| High Speed FIFOs In Spartan-II FPGAs (Xilinx, Inc.) |
| Highest MHz Does Not Mean Highest Performance (Tensilica, Inc.) |
| High-Level "Plug-and-Play" Specification, Modeling and Synthesis of Pipelined Architectures with Bluespec’s PAClib (Bluespec, Inc.) |
| High-Performance DSP Capability within an Optimized Low-Cost FPGA Architecture (Lattice Semiconductor Corp.) |
| Home Networking Using "New Wires" — IEEE 1394, USB, and Fast Ethernet Technologies (Xilinx, Inc.) |
| How a Complete IP Solution Speeds Time-to-Market and Reduces Risk for 10-Gigabit Ethernet Applications (Synopsys, Inc.) |
| How Much Can Logic Perturbation Help from Netlist to Final Routing for FPGAs (49.3) (Design Automation Conference (DAC)) |
| Implementing DSP Designs in Altera Stratix Devices (Mentor Graphics Corp.) |
| Implementing Multipliers with Actel FPGAs (Actel Corp.) |
| Implementing Three-State and Bidirectional Buses with Multiplexers in Actel FPGAs (Actel Corp.) |
| Improving the FPGA Design Process Through Determining and Applying Logical-to-Physical Design Mappings (BYU Configurable Computing Lab) |
| Improving the Performance of a High-Speed Network TCP/IP Traffic Analyzer (Synplicity, Inc.) |
| Incremental Retiming for FPGA Physical Synthesis (Design Automation Conference (DAC)) |
| Information (Internet) Appliances (Xilinx, Inc.) |
| Integrating a PCI Express Digital IP Core into a Gigabit Ethernet Controller (Synopsys, Inc.) |
| Introduction to Actel FPGAs (Actel Corp.) |
| Introduction to Boundary Scan Test and In-System Programming (Lattice Semiconductor Corp.) |
| Introduction to FPGA Technology: Top Five Benefits (National Instruments Corp.) |
| IP Exchange: I'll Show You Mine if You'll Show Me Yours (53.1) (Design Automation Conference (DAC)) |
| Leakage Efficient Chip-Level Dual-Vdd Assignment with Time Slack Allocation for FPGA Power Reduction (Design Automation Conference (DAC)) |
| Leakage Power Reduction of Embedded Memories on FPGAs Through Location Assignment (Design Automation Conference (DAC)) |
| Logic Block Clustering of Large Designs for Channel Width Constrained FPGAs (Design Automation Conference (DAC)) |
| Logical Hardware debuggers for FPGA-based Systems (BYU Configurable Computing Lab) |
| Low-Power USB 2.0 PHY IP for High-Volume Consumer Applications (Synopsys, Inc.) |
| Mapping a Domain Specific Language to a Platform FPGA (Design Automation Conference (DAC)) |
| MATLAB as a Development Environment for FPGA Design (Design Automation Conference (DAC)) |
| Megatrends and EDA 2017 (2.1) (Design Automation Conference (DAC)) |
| Methodologies for Efficient FPGA Integration into PCBs (Xilinx, Inc.) |
| Microprocessor Systems (Xilinx, Inc.) |
| MiniBit: Bit-Width Optimization via Affine Arithmetic (Design Automation Conference (DAC)) |
| Model-based DSP Implementation on FPGAs (University of Maryland (ECE)) |
| Modeling and Implementation of DSP FPGA Solutions (Xilinx, Inc.) |
| Multi-Drop LVDS with Virtex-E FPGAs (Xilinx, Inc.) |
| Multiplexer Restructuring for FPGA Implementation Cost Reduction (Design Automation Conference (DAC)) |
| Multirate Filters and Wavelets: From Theory to Implementation (Xilinx, Inc.) |
| Multi-Resource Aware Partitioning Algorithms for FPGAs with Heterogeneous Resources (Design Automation Conference (DAC)) |
| Nomadic Platform Approach for Wireless Mobile Multimedia (Design Automation Conference (DAC)) |
| Optimal Simultaneous Mapping and Clustering for FPGA Delay Optimization (Design Automation Conference (DAC)) |
| Optimizing FPGAs for High-Volume Applications (Lattice Semiconductor Corp.) |
| PANEL: Structured/Platform ASIC Apprentices: Who Will Survive Your Board Room? (Design Automation Conference (DAC)) |
| Platform Based Design: Does it Answer the Entire SoC Challenge? (Design Automation Conference (DAC)) |
| Power Considerations for USB Applications (QuickLogic Corp.) |
| Power Emulation: A New Paradigm for Power Estimation (Design Automation Conference (DAC)) |
| Predicting the Power Dissipation of Actel FPGAs (Actel Corp.) |
| Processor Core Power Specs: A Cautionary Tale (Tensilica, Inc.) |
| Programmable Platform Solutions (Altera Corp.) |
| RapidChip and HyperTransport Technology (LSI Corp.) |
| RapidChip Platform ASICs vs FPGAs (LSI Corp.) |
| Real Time Image Rotation and Resizing, Algorithms and Implementations (Xilinx, Inc.) |
| Real Time Operating Systems for FPGA (Mentor Graphics Corp.) |
| Real-Time Stereo Vision on the PARTS Reconfigurable Computer (Rapid Prototypes, Inc.) |
| Reconfigurable Computing Application Frameworks (BYU Configurable Computing Lab) |
| Reconfigurable Processors for High-Performance, Embedded Digital Signal Processing (BYU Configurable Computing Lab) |
| Reconfigurable Vehicles (Xilinx, Inc.) |
| Reconfiguration for Reliability Tools (Synplicity, Inc.) |
| Reducing FPGA Costs by Saving a Speed Grade (Mentor Graphics Corp.) |
| Resource-Efficient Acceleration of 2-Dimensional Fast Fourier Transform Computations on FPGAs (University of Maryland (ECE)) |
| Re-timing for Performance Improvement in FPGA Designs (Mentor Graphics Corp.) |
| Reverse Disaggregation: How Silicon IP Will Change the Semiconductor Supply Chain (Synopsys, Inc.) |
| Satisfying the Demand for Rapid Feature Enhancement in Consumer Display Products (Altera Corp.) |
| Selective Bandwidth and Resource Management in Scheduling for Dynamically Reconfigurable Architectures (43.2) (Design Automation Conference (DAC)) |
| Si2 Power Aware Design Flows (Silicon Integration Initiative, Inc. (Si2)) |
| Signal Integrity Comparisons Between Stratix II and Virtex-4 FPGAs (Altera Corp.) |
| Signal Processing at 250 MHz Using High-Performance FPGAs
(Rapid Prototypes. Inc.) |
| Simultaneous Time Slack Budgeting and Retiming for Dual-Vdd FPGA Power Reduction (Design Automation Conference (DAC)) |
| Single Event Upsets in FPGAs (QuickLogic Corp.) |
| Single-Event-Upset (SEU) Awareness in FPGA Routing (18.3) (Design Automation Conference (DAC)) |
| Smart Move: A Placement-Aware Retiming and Replication Method for FPGAs (Mentor Graphics Corp.) |
| Soft CPU Cores for FPGA (1-CORE Technologies) |
| Soft Multipliers for DSP Applications (Altera Corp.) |
| Solving the Challenges for Terabit Networking and Beyond (Xilinx, Inc.) |
| Solving the Integration Challenges for USB-Enabled Designs (Synopsys, Inc.) |
| Straightforward IP Integration with IP-XACT RTL-TLM Switching (IPsupermarket) |
| Stratix II DSP Performance (Altera Corp.) |
| Successfully Designing FPGA-Based Systems (Cadence Design Systems, Inc.) |
| Synchronous Dividers in Actel FPGAs (Actel Corp.) |
| Synthesis of High-Performance Packet Processing Pipelines (Design Automation Conference (DAC)) |
| Synthesizable FPGA Interface for Retrieving ROM Number from 1-Wire Devices (Xilinx, Inc.) |
| Synthesizable Models Enable Early Emulation for Complex IP (Bluespec, Inc.) |
| Test Vector Guidelines (Actel Corp.) |
| The ABC’s of 2.4 and 5 GHz Wireless LANs (Xilinx, Inc.) |
| The Evolution of High-Definition Digital Television (Synplicity, Inc.) |
| The Need for Dynamic Phase Alignment in High-Speed FPGAs (Altera Corp.) |
| The Platform FPGA: Enabling The Software Radio (Xilinx, Inc.) |
| TLM-2.0 in Action: An Example-based Approach to Transaction-Level Modeling and Model Interoperability (Open SystemC Initiative (OSCI)) |
| Traffic Shaping for an FPGA based SDRAM Controller with Complex QoS Requirements (Design Automation Conference (DAC)) |
| Transistor Abstraction for the Functional Verification of FPGAs (Design Automation Conference (DAC)) |
| Trends in the Use of Re-Configurable Platforms (Design Automation Conference (DAC)) |
| Trusted Design in FPGAs (1.2) (Design Automation Conference (DAC)) |
| Understanding the Fundamentals of PCI Express (Synopsys, Inc.) |
| Using Cyclone III FPGAs for Clearer LCD HDTV Implementation (Altera Corp.) |
| Using Cyclone III FPGAs for Emerging Wireless Applications (Altera Corp.) |
| Using Design-Level Scan to Improve Design Observability and Controllability for Functional Verification of FPGAs (BYU Configurable Computing Lab) |
| Using FPGA-Based Simulation Acceleration In a Typical ASIC Design Flow (Aldec, Inc.) |
| Using FPGAs for Digital PLL Applications (Actel Corp.) |
| Using Negative Edge Triggered FFs to Reduce Glitching Power in FPGA Circuits (18.2) (Design Automation Conference (DAC)) |
| Using Programmable Logic for Embedded Systems (Mentor Graphics Corp.) |
| Verilog Tutorial (Yankee Bush Software) |
| VHDL Tutorial (Yankee Bush Software) |
| Video and Image Processing Design Using FPGAs (Altera Corp.) |
| Video Surveillance Implementation Using FPGAs (Altera Corp.) |
| Virtual Memory Window for Application-Specific Reconfigurable Coprocessors (Design Automation Conference (DAC)) |
| VirtualWires: A Technology for Massive Multi-FPGA Systems (Mentor Graphics Corp.) |
| Voice-Data Convergence: Voice Over IP (Xilinx, Inc.) |
| Voltage-Frequency Island Partitioning for GALS-based Networks-on-Chip (8.1) (Design Automation Conference (DAC)) |
| Who Defines the FPGA Interface? (Mentor Graphics Corp.) |
| Wireless Home Networks — DECT, Bluetooth, HomeRF, and Wireless LANs (Xilinx, Inc.) |
