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SOCcentral.com is engaged in a major project to build the most comprehensive directory of EDA tools – and EDA tool vendors – available on the Internet. As we add tools to the directory, they'll be highlighted here so if you see a tool that you're not familiar with, take the time to check it out.
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SOCcentral directory of all EDA tool vendors
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You can also find those vendors listed on SOCcentral that provide a specific category of tools for custom IC, ASIC, FPGA, IP, or PCB design. The selection options are based on the schema developed by industry veteran Gary Smith. Attractive wall charts listing ESL, CAE and CAD-CAM vendors can be downloaded (for free) from Gary Smith EDA.
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Magazine & Journal articles on EDA and EDA tools |
| Reusable Device Simulation Models for Embedded System Virtual Platforms (Design & Reuse) 8/24/2010 |
| SystemVerilog Configurable Coverage Model In an OVM setup: Concept of Reusability (EDA DesignLine) 8/24/2010 |
| An Efficient ASIP Design Methodology (Design & Reuse) 8/16/2010 |
| Comparing AMBA AHB to AXI Bus Using System Modeling (Design & Reuse) 8/16/2010 |
| Data Storage Yields Increased Design Productivity (EDN Magazine) 8/16/2010 |
| FPGA Compilation On-Site or In the Cloud (Programmable Logic DesignLine) 8/16/2010 |
| Picking the Right Built-In Self-test Strategy for Your Embedded ASIC (Embedded Systems Design (embedded.com)) 8/16/2010 |
| Reduce Embedded SOC Design Cost and Optimize IP Integration (Embedded Systems Design (embedded.com)) 8/16/2010 |
| Transaction Analysis and Debug Across Language Boundaries and Between Abstraction Levels (Design & Reuse) 8/16/2010 |
| Using In-Design Physical Verification to Reduce Tape-Out Schedules (Design & Reuse) 8/2/2010 |
| Use XML to Build ASIC or SOC Design Specifications (Embedded Systems Design (embedded.com)) 7/31/2010 |
| Design Quality and Its Impact On Design Closure (EDN Magazine) 7/30/2010 |
| EM Simulation for EMC: Keeping a Lid on Interference (EDN Magazine) 7/30/2010 |
| ESL Synthesis: Tips for Implementing a Viable ESL-Synthesis Flow (EDN Magazine) 7/30/2010 |
| Protect Your goal with Post-Silicon Formal Verification (Design & Reuse) 7/30/2010 |
| Accelerating the Time to IC Layout (EDA DesignLine) 7/29/2010 |
| Customized FPGA board for ASIC Prototyping: A Novel Approach with Pre-designed Blocks and Modular FPGA (Design & Reuse) 7/29/2010 |
| Generating AMD Microcode Stimuli Using VCS Constraint Solver (Design & Reuse) 7/29/2010 |
| IP Re-Engineering and Design Methodology (Design & Reuse) 7/29/2010 |
| Interoperable DRC/LVS Language Standard Accelerates Physical Verification Turnaround Time for Advanced Nodes (EDN Magazine) 7/27/2010 |
| Real-Time Non-intrusive Debugging Framework (Design & Reuse) 7/23/2010 |
| Give the People What They Want: HLS for RTL Verification (EDA DesignLine) 7/21/2010 |
| Debug Will Get Your Attention, Sooner or Later (EDA DesignLine) 6/29/2010 |
| Exploring Multicore Power Management with Modeling and Simulation (Embedded Systems Design (embedded.com)) 6/29/2010 |
| Testing Your MEMS-Based Embedded Design for Hardware Faults (Embedded Systems Design (embedded.com)) 6/29/2010 |
| Time Is Right for Clockless Design (EDA DesignLine) 6/29/2010 |
| Using Standards-Based Tools to Scale Chip Designs to Next-Generation Geometries (Embedded Systems Design (embedded.com)) 6/29/2010 |
| Verifying Your Configurable OCP Interfaces (Embedded Systems Design (embedded.com)) 6/29/2010 |
| Path-Specific Derating to Reduce Timing Pessimism (EDN Magazine) 6/25/2010 |
| How to Make Virtual Prototyping Better than Designing with Hardware: Part 2 - The Importance of Testability In Virtual Prototyping (Embedded Systems Design (embedded.com)) 6/23/2010 |
| SystemVerilog-Based Generic Verification Methodology for IPs/ ASICs/ SOCs (Design & Reuse) 6/23/2010 |
| Testing Embedded Data Buses and Analog Signals (EDN Magazine) 6/23/2010 |
| Efficient C Programming and Its Effect On the Performance of Embedded Systems (Embedded Systems Design (embedded.com)) 6/22/2010 |
| How to Make Virtual Prototyping Better than Designing with Hardware: Part 1 - Use Cases for Virtual Prototyping (Embedded Systems Design (embedded.com)) 6/22/2010 |
| Is IP Integration the Real High-Level Design? (EDN Magazine) 6/21/2010 |
| Achieving Verification Closure with Resource and Time Constraints (EDA DesignLine) 6/17/2010 |
| Advancing Network Packet Management and Security Using Silicon Based Subsystem IP Solutions (Design & Reuse) 6/17/2010 |
| Altering the SOC Design Flow (EDN Magazine) 6/17/2010 |
| Challenges in Verification of Clock Domain Crossings (DAC Knowledge Center) 6/17/2010 |
| Creating Virtual Platforms Using the OCP-IP Modeling Kit (Design & Reuse) 6/17/2010 |
| Low Power: A Chip and System-Design Primer (EDN Magazine) 6/17/2010 |
| Parametric Yield Estimation for SRAM Cells: Concepts, Algorithms and Challenges (DAC Knowledge Center) 6/17/2010 |
| Power Analysis of Clock Gating at RTL (EDA DesignLine) 6/17/2010 |
| Power-Grid Analysis on SOC Graphics Chip Design (EDN Magazine) 6/17/2010 |
| Reducing Switching Power with Intelligent Clock Gating (Programmable Logic DesignLine) 6/17/2010 |
| Timing Closure in 45-nm ASICs Using Statistical Static Timing Analysis Design Methodology (DAC Knowledge Center) 6/17/2010 |
| A Monitor-Based Approach to Verification (TechOnLine, Inc.) 6/2/2010 |
| The Transformation of Silicon to System Design (Electronic Products) 6/1/2010 |
| Transitioning from C/C++ to SystemC in High-Level Design (Embedded Systems Design (embedded.com)) 6/1/2010 |
| Code Coverage Convergence In Configurable IP (Design & Reuse) 5/27/2010 |
| Power Management for Optimal Power Design (EDN Magazine) 5/27/2010 |
| Bringing MEMS Into the IC Design Flow (EDA DesignLine) 5/21/2010 |
| Powering Down: Enabling a Power Regression Flow for SoC Design (Embedded Systems Design (embedded.com)) 5/13/2010 |
| Using Unified Modeling Methods to Reduce Embedded Hardware/ Software Development (Embedded Systems Design (embedded.com)) 5/13/2010 |
| DDGEN: An Automated Device Driver Generation Tool for Embedded Systems (Design & Reuse) 5/3/2010 |
| Doing C-code Generation Better: From Graphical Code to Embedded Target (Embedded Systems Design (embedded.com)) 5/3/2010 |
| Making Source Code Analysis Part of the Software Development Process (Embedded Systems Design (embedded.com)) 4/26/2010 |
| Timing Closure On FPGAs (Programmable Logic DesignLine) 4/22/2010 |
| Software Development Team Collaboration Across Disciplines Using UML/ SysML (Embedded Systems Design (embedded.com)) 4/20/2010 |
| Embedded System Design with Open Source Software: Doing It Right (Embedded Systems Design (embedded.com)) 4/19/2010 |
| Clearing the Hurdles of HLS Adoption (EDA DesignLine) 4/13/2010 |
| Treat Programmable Hardware Design As a High-Level System Task (Embedded Systems Design (embedded.com)) 4/13/2010 |
| Continuous-Time Equalizers Improve High-Speed Serial Links (EDN Magazine) 4/8/2010 |
| Setting Up Hardware Verification Testbenches Using OVM Configuration Classes (Embedded Systems Design (embedded.com)) 4/5/2010 |
| RTL Synthesis Can Accelerate the Entire Implementation Flow (EDA DesignLine) 3/31/2010 |
| 10 Questions to Ask When Choosing a Virtualization Solution (Electronic Engineering Times (EE Times)) 3/22/2010 |
| Greening Multiprocessor Design (EDA DesignLine) 3/22/2010 |
| Swimming In the Channel (EDN Magazine) 3/18/2010 |
| Building Quality Assurance Into Your Hardware: EDA Is Not Enough! (EDA DesignLine) 3/17/2010 |
| Power Delivery Network Design Requires Chip-package-system Co-Design Approach (EDA DesignLine) 3/15/2010 |
| Verification of a USB 3.0 Device IP Core in Multi-Layer SystemC Verification Environment (Design & Reuse) 3/15/2010 |
| ICE Debugging: The End of the Battleship Game (EDA DesignLine) 3/10/2010 |
| Ensuring the Thermal Integrity of Your IC Package/ PC Board Design (Power Management DesignLine) 3/8/2010 |
| Hardware Solutions to the Challenges of Multimedia IP Functional Verification (Design & Reuse) 2/25/2010 |
| Software Architecture for IP verification in Operating System Environment (Design & Reuse) 2/25/2010 |
| Dodging Amdahl's Law with Message Passing, FPGA-Based Parallel Processing (Programmable Logic DesignLine) 2/24/2010 |
| Combating Congestion In High-performance, Low-cost SOCs (EDN Magazine) 2/23/2010 |
| High-Level Synthesis, Verification and Language (EDA DesignLine) 2/22/2010 |
| Tuning C/C++ Compilers for Optimal Parallel Performance In Multicore Applications: The Compiler Optimization Process - Part 2 (Embedded Systems Design (embedded.com)) 2/21/2010 |
| Analog and Mixed-Signal Modeling Approaches (Design & Reuse) 2/18/2010 |
| Tuning C/C++ Compilers for Optimal Parallel Performance In Multicore Applications - Part 1 (Embedded Systems Design (embedded.com)) 2/18/2010 |
| Static Verification: What’s Old Is New Again (SCDsource) 2/17/2010 |
| Chip Synthesis: A New Approach to RTL Implementation (EDA DesignLine) 2/16/2010 |
| Integrating Static Analysis with a Compiler and Database (Embedded Computing Design) 2/16/2010 |
| Guidelines for Complex SOC Verification (EDA DesignLine) 2/15/2010 |
| Re-Configurable Platform for Design, Verification and Implementation of SOCs (Design & Reuse) 2/11/2010 |
| Using Formal Verification for SOC Integration (SCDsource) 2/11/2010 |
| Debugging and Analysis with SystemVerilog Testbench (EDN Magazine) 2/4/2010 |
| Tools Accurately Simulate Noise in Mixed-Signal ASICs (EDN Magazine) 2/4/2010 |
| When Good Compilers Go Bad, or What You See Is Not What You Execute (Embedded Systems Design (embedded.com)) 2/3/2010 |
| Automating Next-Generation Network-Design Tasks (Embedded Systems Design (embedded.com)) 2/2/2010 |
| Improving Software Development and Verification Productivity Using IP-Based System Prototyping (Design & Reuse) 2/1/2010 |
| Waving Goodbye to Phantom DRC Errors (SCDsource) 1/27/2010 |
| A Recipe for Verification IP: The Role of Methodology (Design & Reuse) 1/26/2010 |
| Embedded System Virtualization for Executable Specifications and Use Case Modeling (EDA DesignLine) 1/26/2010 |
| Design for Diagnosis to Improve IC Yield (EDA DesignLine) 1/25/2010 |
| Applying Virtual System Integration and Test to Validate Requirements and Verify Designs (EDA DesignLine) 1/22/2010 |
| Early Verification Cuts Design Time and Cost In Algorithm-intensive Systems (EDA DesignLine) 1/22/2010 |
| Methodology for Rapid Development of Loosely Timed and Approximately Timed TLM Peripherals (Design & Reuse) 1/21/2010 |
| Automating the FPGA Design Debug Process (Embedded Systems Design (embedded.com)) 1/19/2010 |
| Low-power LDPC Decoder Created Using High-Level Synthesis (EDA DesignLine) 1/13/2010 |
| A Real Solution for Mixed Signal SOC Verification (EDA DesignLine) 1/7/2010 |
| Under the Lid: Analog Test Is Suddenly the Critical Ingredient (EDN Magazine) 1/7/2010 |
| Determine IC Transient Thermal Behavior to Prevent Overheating (EDN Magazine) 1/6/2010 |
| Using OVM to Reuse Vital Verification Knowledge (EDA DesignLine) 1/5/2010 |
| How Do You Qualify Netlist Reduction and Circuit Extraction? (EDA DesignLine) 1/4/2010 |
| Reduce Handset EMI to Prevent Receiver-Desense Problems (EDN Magazine) 12/16/2009 |
| Model-Based Design and Early Verification Aid Designers (EDN Magazine) 12/15/2009 |
| Removing Bottlenecks from Your SOC Design-for-Test Flows (EDA DesignLine) 12/14/2009 |
| In-Design Metal-Fill Key to Physical-Verification Turn-Around Time for Advanced IC Designs (EDA DesignLine) 12/8/2009 |
| Why, When and How: The basics of Embedded Systems Prototyping (Embedded Systems Design (embedded.com)) 12/8/2009 |
| Why, When and How: The Basics of Embedded Systems Prototyping (Embedded Systems Design (embedded.com)) 12/8/2009 |
| Improve Functional Verification Quality with Mutation-Based Code Coverage (Embedded Systems Design (embedded.com)) 12/7/2009 |
| Clock Gating: Smart Use Ensures Smart Returns (EDN Magazine) 12/4/2009 |
| Easier Cross-Domain Signal Protection for Mixed-Signal SoCs (EDA DesignLine) 12/4/2009 |
| FPGA Synthesis Can Be a Leverage Point In Your Design Flow (Programmable Logic DesignLine) 12/2/2009 |
| ESL Tools Take Center Stage As Designers Move Up (Electronic Design Magazine) 12/1/2009 |
| The Best of Both Worlds: Optimizing OCP Slave Memory Behavior (EDA DesignLine) 11/19/2009 |
| Tackling System Design Challenges Through Early Verification (Electronic Design Magazine) 11/17/2009 |
| SaaS and EDA: Are Designers Ready? (Electronic Engineering Times (EE Times)) 11/16/2009 |
| Use Formal, Online Communication to Deliver Design Quality Closure (Electronic Engineering Times (EE Times)) 11/16/2009 |
| Using Formal for Design Space Exploration (SCDsource) 11/16/2009 |
| Boundary Scan and JTAG Emulation Combine for Advanced Structural Test and Diagnostics (Embedded Systems Design (embedded.com)) 11/10/2009 |
| An UML-Driven Interface Generation Approach for SoC Design (Design & Reuse) 11/2/2009 |
| Calculating Corner Independent Timing Closure (Embedded Systems Design (embedded.com)) 10/30/2009 |
| Adding Hardware Acceleration to the HVL Testbench (Design & Reuse) 10/29/2009 |
| Debugging FPGA Designs May Be Harder than You Expect (EDN Magazine) 10/22/2009 |
| FPGA-Based Rapid Prototyping of ASIC, ASSP, and SoC Designs (Programmable Logic DesignLine) 10/21/2009 |
| How to Reduce Memory Power in SOC Designs (EDA DesignLine) 10/15/2009 |
| Using Formal to Verify Complex Reset Schemes (SCDsource) 10/4/2009 |
| A Brief Introduction to the TCL Scripting Language (Embedded Systems Design (embedded.com)) 10/2/2009 |
| Using Tcl to Create a Virtual Component in Verilog (Embedded Systems Design (embedded.com)) 10/2/2009 |
| Getting to the Roots of the Eclipse Integrated Development Environnment (Embedded Systems Design (embedded.com)) 9/1/2009 |
| Improving Software Driver Development and Hardware Verification Productivity using Virtual Platforms (Design & Reuse) 8/27/2009 |
| Timing Annotation of Untimed Functional Models for Architecture Use-Case (Design & Reuse) 8/27/2009 |
| Debugging Hardware Designs with an FPGA-Based Emulation Tool (Embedded Systems Design (embedded.com)) 8/24/2009 |
| Fast Design Productivity for Embedded Multiprocessor through Multi-FPGA Emulation (Design & Reuse) 8/20/2009 |
| Take Advantage of Open-Source Hardware (EDN Magazine) 8/20/2009 |
| Virtual Testing with Model-Based Design (Industrial Control DesignLine) 8/17/2009 |
| Verification and Generation of Constraints (Design & Reuse) 8/13/2009 |
| The Virtual Vehicle: Making Power Management Easier (EDA DesignLine) 8/11/2009 |
| Techniques for Implementing High-Performance Processor Cores (EDN Magazine) 8/6/2009 |
| Tackling the Non-Technical Challenges in the Design of Manufacturing Processes (EDA DesignLine) 8/3/2009 |
| Changing SoC Design Methodologies to Automate IP Integration and Reuse (EDA DesignLine) 7/27/2009 |
| Formal Methodology Validates Cache-Coherence Protocol (Electronic Design Magazine) 7/23/2009 |
| Making ASIC Power Estimates Before the Design (EDN Magazine) 7/23/2009 |
| Programmable Chips: Piecing Together an Analog Solution (EDN Magazine) 7/23/2009 |
| Bridging from ESL Models to Implementation Via High-level Hardware Synthesis (EDA Tech Forum) 7/15/2009 |
| Computational Scaling: Implications for Design (EDA Tech Forum) 7/15/2009 |
| Parallel Transistor-Level Full-Chip Circuit Simulation (EDA Tech Forum) 7/15/2009 |
| Using TLM Virtual System Prototype for Hardware and Software Validation (EDA Tech Forum) 7/15/2009 |
| Barriers to Widescale Acceptance of Assertion-based Verification (Electronic Engineering Times (EE Times)) 7/13/2009 |
| Parasitic Extraction: 3D or Not 3D, That Is the Question (Electronic Engineering Times (EE Times)) 7/13/2009 |
| Power Verification: Trust But Verify, Or Verify and Trust? (Electronic Engineering Times (EE Times)) 7/13/2009 |
| Software-to-Silicon Verification @ 45nm and beyond (Electronic Engineering Times (EE Times)) 7/13/2009 |
| Unleash the Power of Formal Technology for CDC Verification (Electronic Engineering Times (EE Times)) 7/13/2009 |
| Early Verification and Validation Using Model-Based Design (EDN Magazine) 7/9/2009 |
| EDA Companies Tout RF Design, Links to Test (EDN Magazine) 7/9/2009 |
| FPGA Verification in Embedded Video-Processing Systems (EDN Magazine) 7/9/2009 |
| High-Level Software for Embedded-System Design Doing Your Job? (EDN Magazine) 7/9/2009 |
| Tackling Formal Assumptions Through Verification Planning (EDN Magazine) 7/7/2009 |
| Debugging Hybrid FPGA Logic/Processor Designs (Electronic Products) 7/1/2009 |
| Five Top Practices for Better Test Software (Electronic Products) 7/1/2009 |
| Mobile Device Security Through Virtualization (EDN Magazine) 7/1/2009 |
| Synthesis Needs to Change to Serve Modern Chip Design (Electronic Products) 7/1/2009 |
| Rapid Debug of Serial Buses in FPGAs (Embedded Systems Design (embedded.com)) 6/30/2009 |
| Should Dual-Rail Go Mainstream in Deep Nanometer Era? (Electronic Design Magazine) 6/29/2009 |
| Examining the Case for Analog Automation (Electronic Engineering Times (EE Times)) 6/22/2009 |
| Managing an Adaptive Verification Environment with the Open Verification Methodology (Design & Reuse) 6/22/2009 |
| EDA Remains the Enabler of Much-Needed Innovation (Electronic Design Magazine) 6/18/2009 |
| Generic and Automatic Specman-based Verification Environment for Image Signal Processing IPs (Design & Reuse) 6/18/2009 |
| SpiritEd: A Register Specification System integrating IP-XACT and Adobe FrameMaker (Design & Reuse) 6/18/2009 |
| Design for Manufacturing Sheds the Hype (Electronic Design Magazine) 6/11/2009 |
| Troubleshooting a Transaction-Level Model (EDN Magazine) 6/11/2009 |
| FPGA the Holistic Way: Flow Integration from Concept to PCB (FPGA and Programmable Logic Journal) 6/9/2009 |
| Power Management: Parametric Design By Software (Power Management DesignLine) 6/7/2009 |
| Validating Advanced Foundry Models (SCDsource) 6/4/2009 |
| Advantages of Isotropic PCB Routing (Printed Circuit Design & Fab) 6/1/2009 |
| Debugging Software/Firmware Using Trace Function Re-Usable Components (Embedded Systems Design (embedded.com)) 6/1/2009 |
| Fan-Out Strategies for Fine-Pitch BGAs (Printed Circuit Design & Fab) 6/1/2009 |
| Improving Via Design for High Data Rate Applications (Printed Circuit Design & Fab) 6/1/2009 |
| HDL Design Methods for Low-Power Implementation (Design & Reuse) 5/28/2009 |
| High-Level Synthesis of JPEG Application Engine (Design & Reuse) 5/25/2009 |
| Apply Virtualization to Storage I/O (Electronic Design Magazine) 5/21/2009 |
| Keeping Up with Changes In Semiconductor Validation with PXI (Embedded Systems Design (embedded.com)) 5/18/2009 |
| Making the Case for a New Approach to FPGA Debugging and Validation (DSP-FPGA) 5/15/2009 |
| Need to Cut Cost, Risk, Time? Choose the Right FPGA Design Solution (FPGA and Programmable Logic Journal) 5/12/2009 |
| Using Advanced Logging Techniques to Debug and Test SystemVerilog HDL Code (Embedded Systems Design (embedded.com)) 5/12/2009 |
| Comparing AMBA AHB to AXI Buses Using System Modeling (SCDsource) 5/5/2009 |
| Accuracy of Transmission Line Simulators (Printed Circuit Design & Fab) 5/1/2009 |
| S-Parameters for Digital Designers (Printed Circuit Design & Fab) 5/1/2009 |
| Automated Formal Method Verifies Highly-configurable HW/SW Interface (SCDsource) 4/30/2009 |
| Mixing Formal and Dynamic Verification: Part 1 (SCDsource) 4/30/2009 |
| Estimating Power in FPGA Designs (EDN Magazine) 4/23/2009 |
| Protecting Software IP: What Engineers Need to Know (Electronic Engineering Times (EE Times)) 4/20/2009 |
| Incremental Synthesis: Achieving Shorter Design Cycles without Quality Trade-Offs (FPGA and Programmable Logic Journal) 4/14/2009 |
| What You Need to Know About Automated Testing and Simulation (Embedded Systems Design (embedded.com)) 4/14/2009 |
| Online Tools Home In on Analog Design (EDN Magazine) 4/9/2009 |
| Board-Level Timing Analysis (EDA Tech Forum) 4/1/2009 |
| Bridging the ECAD-MCAD Gap (EDA Tech Forum) 4/1/2009 |
| Concurrent RF/ Microwave PCB Design (Printed Circuit Design & Fab) 4/1/2009 |
| Learning the Value of Preparation and Simulation by OSMOSIS (EDA Tech Forum) 4/1/2009 |
| More Efficient Board Design for RF, Analog and Digital (EDA Tech Forum) 4/1/2009 |
| Rapid Embedded Design Requires High-Level Tools (Electronic Products) 4/1/2009 |
| Reducing PCB Design Cycle By 60% (EDA Tech Forum) 4/1/2009 |
| Multicore Programming: Easy or Difficult? (EDN Magazine) 3/25/2009 |
| Establishing Timing Correlation Between Tools (EDN Magazine) 3/19/2009 |
| How Physical Synthesis Enables FPGA Design Productivity (FPGA and Programmable Logic Journal) 3/17/2009 |
| Integrated Power Management, Leakage Control and Process Compensation Technology for Advanced Processes (Design & Reuse) 3/16/2009 |
| A Synthesis and Partitioning Strategy for Effective Multi-FPGA Prototyping (FPGA and Programmable Logic Journal) 3/10/2009 |
| Debug and Testability Features for Multi-Protocol 10G SerDes (Design & Reuse) 3/9/2009 |
| Functional Qualification: A Technical Brief (Programmable Logic DesignLine) 3/2/2009 |
| IC Package to PCB Co-Design (Printed Circuit Design & Fab) 3/1/2009 |
| Manufacturing Compliance: It’s Your Job (Printed Circuit Design & Fab) 3/1/2009 |
| Behavioral Design Drives Low-Power Silicon (EDA DesignLine) 2/16/2009 |
| Is ESL Adoption Really All That Difficult? (Electronic Design Magazine) 2/12/2009 |
| Abstraction and Control-Dominated Hardware Designs (EDA DesignLine) 2/6/2009 |
| Statistical Static Timing Analysis: A Better Alternative (EDA DesignLine) 2/3/2009 |
| EDA Bashing (EDA DesignLine) 2/2/2009 |
| E-Beam Technology Breaks Through Complex Design Cycles (Semiconductor International) 2/1/2009 |
| How SLEC Improves Functional Verification (EDA DesignLine) 1/23/2009 |
| Simulation Gets Speed, Capacity Boost (EDN Magazine) 1/22/2009 |
| Jasper, OneSpin Seek Broader Audience for Formal Verification Tools (EDN Magazine) 1/21/2009 |
| What’s In a System? (Electronic Design Magazine) 1/21/2009 |
| Filter Banks, Part 1: Principles and Design Techniques (DSP DesignLine) 1/15/2009 |
| Architecting the OCP uVC Verification Component (EDA DesignLine) 1/13/2009 |
| Doing ESL System Validation Using Transactors (Embedded Systems Design (embedded.com)) 1/13/2009 |
| Expanding Efficiency with Rapid Prototyping (Embedded Systems Design (embedded.com)) 1/13/2009 |
| Virtual Systems Link ESL, Model-Driven Engineering (SCDsource) 1/13/2009 |
| Using Yesterday's Methodologies to Design Today'S Multi-FPGA Systems Is a Recipe for Disaster (Programmable Logic DesignLine) 1/7/2009 |
| Automating the DDRx Interface Verification Process (Printed Circuit Design & Fab) 1/1/2009 |
| Combining Yield and Performance in Behavioral Models for Analog ICs (EDA Tech Forum) 12/31/2008 |
| Finding the Right Partner (EDA Tech Forum) 12/31/2008 |
| From GDSII to Oasis (EDA Tech Forum) 12/31/2008 |
| IP Hardens Up Again (EDA Tech Forum) 12/31/2008 |
| License to Profit: Managing Your Software Assets Is a Pervasive Bottom Line Issue (EDA Tech Forum) 12/31/2008 |
| OCP Performance Monitoring with Programmable Instruments (EDA Tech Forum) 12/31/2008 |
| Tightening the Loop on Coverage Closure (EDA Tech Forum) 12/31/2008 |
| Verification IP: Solace for the Common Integration Nightmare? (New Tech Press) 12/24/2008 |
| Chip/ Package/ PCB Co-simulation: What It Is, Why It's Needed (SCDsource) 12/16/2008 |
| Formal Verification Enables Safe X Handling (SCDsource) 12/16/2008 |
| Planning, Adopting and Implementing Adaptive Reuse (EDA DesignLine) 12/16/2008 |
| Ten 2009 Trends in System and Chip Design (SCDsource) 12/16/2008 |
| Use Algorithmic Synthesis to Solve Your FPGA Prototyping and Design Issues (Electronic Design Magazine) 12/10/2008 |
| Algorithmic Synthesis for Video Post-Processor Design (EDA DesignLine) 12/9/2008 |
| Golden Timing Signoff - Does It Correlate to Spice? (SCDsource) 12/7/2008 |
| Prototyping Techniques: Things to Know Before Pulling the Trigger (EDN Magazine) 12/5/2008 |
| Verification Metrics: When is Enough Enough? (EDN Magazine) 12/5/2008 |
| Minimizing the Pain of RTL Design Reviews (FPGA and Programmable Logic Journal) 11/25/2008 |
| Unified Verification for Hardware and Embedded Software Developers (EDA DesignLine) 11/25/2008 |
| Packaging Goes Vertical (Electronic Engineering Times (EE Times)) 11/24/2008 |
| 3-D Integration Lacking in Design and Test Support (Semiconductor International) 11/18/2008 |
| Planning, Adopting and Implementing Adaptive Reuse (EDA DesignLine) 11/18/2008 |
| TLM 2.0 Promising, But Interoperability Isn’t Proven (SCDsource) 11/13/2008 |
| Bulletproof Your System Timing with Programmable Clocks (Electronic Design Magazine) 11/7/2008 |
| 3D Chip-Package-Board Modeling (Printed Circuit Design & Fab) 11/4/2008 |
| A SystemC/TLM Based Methodology for IP Development and FPGA Prototyping (EDA DesignLine) 11/3/2008 |
| Improving Circuit Simulation with the Addition of Real Measurements (Printed Circuit Design & Fab) 11/1/2008 |
| Tips to Improve Manufacturability (Printed Circuit Design & Fab) 11/1/2008 |
| Opportunities in Analog Verification (EDA DesignLine) 10/28/2008 |
| Virtual Prototypes Speed Wireless Development (Electronic Engineering Times (EE Times)) 10/27/2008 |
| The Role of JTAG in System Debug and Test (Embedded Systems Design (embedded.com)) 10/22/2008 |
| A Turn-off: Power Management Complicates Life for Verification Engineers (EDN Magazine) 10/16/2008 |
| EDA Needs Functional Qualification (Electronic Engineering Times (EE Times)) 10/7/2008 |
| Reducing Power in High-Performance Designs (Chip Estimate Corp.) 10/7/2008 |
| Tool Integration for ESL Design (FPGA and Programmable Logic Journal) 10/7/2008 |
| The Need to Address Power During Manufacturing Test (EDA DesignLine) 10/6/2008 |
| CAM/CAD Design Rules and Guidelines (CircuiTree) 10/1/2008 |
| Mixed-Signal Design Considerations (Printed Circuit Design & Fab) 10/1/2008 |
| Taking the Broad View (Components in Electronics (CIE)) 10/1/2008 |
| The New Wave in High-Speed Modeling (Printed Circuit Design & Fab) 10/1/2008 |
| FPGA Timing Closure: The Whack-a-Mole Game (FPGA and Programmable Logic Journal) 9/30/2008 |
| How Equation-Based DRC Solves Design/ Manufacturing Challenges (SCDsource) 9/16/2008 |
| Selecting the Right FPGA Synthesis Tool (FPGA and Programmable Logic Journal) 9/16/2008 |
| The Embedded Plan for JTAG Boundary Scan (Electronic Design Magazine) 9/11/2008 |
| Building a Configurable Embedded Processor (Embedded Systems Design (embedded.com)) 9/9/2008 |
| Reducing Power Consumption in a Fiber Channel Switch (EDA DesignLine) 9/9/2008 |
| Handcrafted Analog Gets Automated Assist (EDN Magazine) 9/4/2008 |
| Automating Low-Power Design: A Progress Report (SCDsource) 9/3/2008 |
| Formal Verification Checks IC Power-Reduction Features (SCDsource) 9/3/2008 |
| Improving Statistical Design for Analog/ Custom Circuits (SCDsource) 9/2/2008 |
| Embedded Instrumentation and Boundary Scan (Electronic Products) 9/1/2008 |
| Product Development Efficiency Through ECAD-MCAD Collaboration (EDA Tech Forum) 9/1/2008 |
| Dev Kits Help Alleviate Those FPGA Design Woes (Electronic Design Magazine) 8/28/2008 |
| Eye-Diagram Analysis Speeds DDR SDRAM Validation (Electronic Design Magazine) 8/28/2008 |
| Electronic System Level Design: Is There Fire Beneath the Smoke? (EDN Magazine) 8/21/2008 |
| Learning Not to Fear PCI Express Compliance (EDA DesignLine) 8/12/2008 |
| Going from GDSII to OASIS (EDA DesignLine) 8/4/2008 |
| Virtualization for Embedded X86 Multiprocessor Applications (Embedded Systems Design (embedded.com)) 8/3/2008 |
| How High-Level Modeling Speeds Low-Power Design (SCDsource) 7/29/2008 |
| Make Virtualization Work for Mobile Devices (Mobile Handset DesignLine) 7/25/2008 |
| Floorplanning a Power Delivery Network with Spice (Electronic Design Magazine) 7/24/2008 |
| HDL-Design Challenges and Philosophies for Real-World ASIC Implementations (EDN Magazine) 7/24/2008 |
| Spread Spectrum Clock generators Reduce EMI and Signal Integrity Problems (EDN Magazine) 7/24/2008 |
| Using Formal Verification for FPGA Designs (SCDsource) 7/22/2008 |
| Achieve Femtoampere Leakage in Surface-mount Op-Amp Layouts (EDN Magazine) 7/18/2008 |
| Periodic Steady-State and Small-Signal Analyses of Switching Regulators (EDN Magazine) 7/18/2008 |
| Architectural Templates Power Algorithmic Synthesis (SCDsource) 7/15/2008 |
| Modeling Cost, Availability Ups ESL Return on Investment (SCDsource) 7/15/2008 |
| Measurement-Based Simulation Simplifies Analysis of Lossy Backplanes and Cables (EDN Magazine) 7/10/2008 |
| Where Is EDA Going Now? (EDN Magazine) 7/10/2008 |
| ESL Handoff: Closer Than You Think (EDA DesignLine) 7/8/2008 |
| How to Overcome the Increasing Management Complexity of FPGA/PCB Pin Synchronization (Programmable Logic DesignLine) 7/2/2008 |
| Reducing Time in IC Physical Verification (SCDsource) 7/1/2008 |
| Optimize IC Power By Understanding Circuit Activity (SCDsource) 6/24/2008 |
| Why SystemC Virtual Platforms Are the Answer (SCDsource) 6/24/2008 |
| Achieving First-time Success at 40nm (EDN Magazine) 6/12/2008 |
| EDA Sales Shouldn't Be Like Buying a Used Car (SCDsource) 6/10/2008 |
| Bridging the Gap Between Silicon and Software Validation (EDA DesignLine) 6/6/2008 |
| Making the Move to ESL Hardware Design (EDA Tech Forum) 6/1/2008 |
| Multi-Corner Multi-Mode Signal Integrity Optimization (EDA Tech Forum) 6/1/2008 |
| VHDL Moves Toward 4.0 (EDA Tech Forum) 6/1/2008 |
| Avoid FPGA Project Delays by Adopting Advanced Design Methodologies (FPGA and Programmable Logic Journal) 5/27/2008 |
| Best Practices Emerge for Multicore Programming (SCDsource) 5/22/2008 |
| Modeling Copper Concentrations Improves PCB Thermal Simulation (SCDsource) 5/20/2008 |
| Preserving the Intent of Timing Constraints (EDA DesignLine) 5/17/2008 |
| How to Raise the RTL Abstraction Level and Design Conciseness with SystemVerilog: Part 2 (Programmable Logic DesignLine) 5/14/2008 |
| Characterizing Nanometer CMOS PLLs, Sigma-Delta ADCs and AGCs (EDA DesignLine) 5/13/2008 |
| FPGA Design Requires Low-Power Techniques (SCDsource) 5/6/2008 |
| Host Bus Adapter (HBA) Verification (EDA DesignLine) 5/6/2008 |
| How Floorplanning Guides Synthesis and Physical Design (SCDsource) 5/6/2008 |
| How to Raise the RTL Abstraction Level and Design Conciseness with SystemVerilog: Part 1 (Programmable Logic DesignLine) 4/30/2008 |
| How to Implement SystemVerilog for FPGA Design (FPGA and Programmable Logic Journal) 4/29/2008 |
| Open Verification Methodology Allows Reusable Testbenches (SCDsource) 4/29/2008 |
| New Standards Effort Targets Verification IP Interoperability (SCDsource) 4/28/2008 |
| Using Formal Verification for Post-Silicon Debug (SCDsource) 4/23/2008 |
| What Floorplan Information Is Needed for Synthesis (EDA DesignLine) 4/22/2008 |
| Interfacing High-Speed Data Converters (EDN Magazine) 4/18/2008 |
| C-Based Coprocessor Design, Part 1: SIMD Architecture (DSP DesignLine) 4/17/2008 |
| Virtual Prototyping Boosts Model-Driven Design for Six Sigma methodology, Part 2 of 3: Process Integration Keys Quality (Automotive DesignLine) 4/17/2008 |
| Validating False Path Timing Exceptions (SCDsource) 4/15/2008 |
| Virtualization and Hypervisors Aid Embedded Design (Electronic Products) 4/14/2008 |
| Multi-language Functional Verification Coverage for Multi-Site Projects (EDA DesignLine) 4/12/2008 |
| Virtual Prototyping Boosts Model-Driven "Design for Six Sigma" Methodology, Part 1 of 3: The Challenges and Tools (Automotive DesignLine) 4/9/2008 |
| Critical Clock-Domain-Crossing Bugs (EDN Magazine) 4/2/2008 |
| Intelligent Parasitic Extraction with Fast Spice Verification (SCDsource) 4/2/2008 |
| Improving Fabrication Yields By Design (Printed Circuit Design & Fab) 4/1/2008 |
| Open Verification Methodology: Why Now? (EDA DesignLine) 4/1/2008 |
| Solve Design Problems with Signal Integrity Optimization (Printed Circuit Design & Fab) 4/1/2008 |
| Software-Defined Radio Platforms (EDA DesignLine) 3/24/2008 |
| Statistical Timing Gets a Foothold in Leading-edge Designs (EDN Magazine) 3/24/2008 |
| Trip Points for IC Timing Analysis (EDN Magazine) 3/20/2008 |
| Using IC Prototyping to Optimize Design Implementation (EDN Magazine) 3/20/2008 |
| Fast Transient Noise Analysis for PLLs and ADCs (SCDsource) 3/19/2008 |
| Design for Low-Power Manufacturing Test (EDA DesignLine) 3/18/2008 |
| How to Specify and Verify Power-Cycled SOCs for Checking and Coverage (EDN Magazine) 3/18/2008 |
| FPGA-Based Prototyping Grows Up (Electronic Engineering Times (EE Times)) 3/10/2008 |
| Verify SOCs Faster and More Predictably with SystemVerilog and Constrained- Random Stimuli (Electronic Design Magazine) 3/5/2008 |
| Intelligent Testbench Automation Boosts Verification Productivity (SCDsource) 3/4/2008 |
| Low-Power Design for Analog/Mixed-Signal IP (EDA DesignLine) 3/4/2008 |
| No Simple Equation for Verification Success (SCDsource) 2/27/2008 |
| Complex SOC Testing with a Core-Based DFT Strategy (EDA DesignLine) 2/26/2008 |
| As SOCs Grow, Test-and-Measurement Instruments Move On-Chip (EDN Magazine) 2/21/2008 |
| VMM Application Packages: The Next Level of Productivity (EDN Magazine) 2/21/2008 |
| Three Verification Improvements Boost Functional Coverage (SCDsource) 2/20/2008 |
| SystemVerilog is Coming to FPGA Design (FPGA and Programmable Logic Journal) 2/19/2008 |
| Multi-language Functional Verification Coverage for Multi-site Projects (EDA DesignLine) 2/18/2008 |
| Power-Intent Standards Vie for Designers' Loyalties (Electronic Design Magazine) 2/14/2008 |
| Effectively Using Internal Logic Analyzers for Debugging FPGAs (FPGA and Programmable Logic Journal) 2/12/2008 |
| Simplifying PLL Design (EDA DesignLine) 2/12/2008 |
| Hardware Design Using ESL (Electronic Engineering Times (EE Times)) 2/11/2008 |
| An RTL Solution to Test Integration Challenges (SCDsource) 2/6/2008 |
| Physically Aware Test Development (EDA DesignLine) 2/5/2008 |
| FPGA-Based Prototyping: "Productivity to Burn" (Programmable Logic DesignLine) 1/30/2008 |
| Probabilistic Approach Helps Ensure DFM Success (SCDsource) 1/30/2008 |
| Power Integrity and Energy-Aware Floor Planning (EDA DesignLine) 1/29/2008 |
| How to Achieve Timing-Closure in High-End FPGAs (Programmable Logic DesignLine) 1/23/2008 |
| Why ESL Startups Can't Get Good Valuations (SCDsource) 1/23/2008 |
| Three "I"s of FPGA Design: Iterations, Incremental and Intelligent Design Tools (FPGA and Programmable Logic Journal) 1/22/2008 |
| Automated Formal Verification of OCP-Based IP Cores (EDA DesignLine) 1/21/2008 |
| New Approach to FPGA Physical Synthesis for Ease-of-Use and Wide Device Support (FPGA and Programmable Logic Journal) 1/18/2008 |
| Coverage-Driven Verification for Mixed-Signal Systems (SCDsource) 1/16/2008 |
| Utilizing Clock-Gating Efficiency to Reduce Power (EDA DesignLine) 1/15/2008 |
| Rethinking How to Decrease Power Consumption (EDN Magazine) 1/10/2008 |
| Analyzing IC Power at the Electronic System Level (SCDsource) 1/9/2008 |
| On-chip Validation Extends IC Verification (SCDsource) 1/9/2008 |
| The Art of FPGA Construction (Embedded Systems Design (embedded.com)) 1/6/2008 |
| Dealing with the Challenges of Integrating Hardware and Software Verification (Embedded Systems Design (embedded.com)) 1/4/2008 |
| Achieving Success with Algorithmic Synthesis (SCDsource) 1/2/2008 |
| Verification Platform for Complex Designs (EDA DesignLine) 12/31/2007 |
| Understanding Clock Domain Crossing Issues (EDA DesignLine) 12/24/2007 |
| Choosing and Using the Right Tools for High-speed Serial Data Analysis (Embedded Systems Design (embedded.com)) 12/19/2007 |
| Achieving Yield in the Nanometer Age (EDA DesignLine) 12/17/2007 |
| Applying Constrained-Random Verification to Microprocessors (EDA DesignLine) 12/10/2007 |
| Virtually Every ASIC Ends Up an FPGA (Electronic Engineering Times (EE Times)) 12/7/2007 |
| A Revolution in Functional Verification (Electronic Engineering Times (EE Times)) 12/6/2007 |
| Using DFM Routing to Impact Design Performance and Yield (EDA DesignLine) 12/4/2007 |
| Case Study of a Complex Video System-on-Chip (Electronic Engineering Times (EE Times)) 12/3/2007 |
| Leveraging C/C++ System Models for RTL Functional Verification (Electronic Engineering Times (EE Times)) 12/3/2007 |
| Understanding Coverage with Multiple Verification Methods (SCDsource) 11/28/2007 |
| The Great EDA Cover-Up (EDA DesignLine) 11/26/2007 |
| Physical Synthesis Flows for FPGA Designs (FPGA and Programmable Logic Journal) 11/20/2007 |
| Designers Highlight Challenges of High-Speed I/O (SCDsource) 11/14/2007 |
| PDF CEO Calls for Restricted Layouts (SCDsource) 11/12/2007 |
| Design with Verification: Not an Oxymoron (EDA DesignLine) 11/5/2007 |
| OpenAccess Expands to New Horizons (SCDsource) 11/5/2007 |
| CoWare's ESL 2.0 Upgrade Targets Wide User Base (SCDsource) 11/4/2007 |
| Duct Tape, FPGAs, and the Art of Making Great Multi-Purpose Tools (FPGA and Programmable Logic Journal) 10/30/2007 |
| Accellera VHDL Standard (EDA DesignLine) 10/25/2007 |
| Berkeley ABC Project Reshapes Logic Synthesis (SCDsource) 10/24/2007 |
| Ensuring Power Designing Works at 65nm (EDA DesignLine) 10/22/2007 |
| Make Front-End Power Predictable (EDN Magazine) 10/19/2007 |
| RTL-ers Should Move to ESL (eeDesign (EE Times EDA News)) 10/19/2007 |
| In-System Silicon Validation and Debug: Part 3, Silicon Experience (EDA DesignLine) 10/15/2007 |
| Sign-Off for Manufacturability (EDA DesignLine) 10/8/2007 |
| 4G Wireless: Evolution or Watershed in SOC Architectures? (EDN Magazine) 10/4/2007 |
| In-System Silicon Validation and Debug: Part 2, the New Approach (EDA DesignLine) 10/2/2007 |
| A New Approach to In-System Silicon Validation and Debug: Part 1, the Problem (EDA DesignLine) 9/16/2007 |
| How Low Can You Go? A Look at 45-nm IC Design Challenges (EDN Magazine) 9/13/2007 |
| Process Intelligent Modeling and Statistical STA improve DFM (EDA DesignLine) 9/11/2007 |
| Top-down DSP Design for FPGAs (Programmable Logic DesignLine) 9/5/2007 |
| TDR and S-parameter Measurements: How Much Performance Do You Need? (EDN Magazine) 9/3/2007 |
| TDR: Taking the Pulse of Signal Integrity (EDN Magazine) 9/3/2007 |
| Power-Sensitive 65-nm Designs Increase the Need for Transistor-Level Verification (EDA DesignLine) 8/27/2007 |
| A Bluespec Hardware Implementation of Sudoku (EDA DesignLine) 8/21/2007 |
| Design Tool Evolution (FPGA and Programmable Logic Journal) 8/21/2007 |
| Design For Manufacturing: Still not Ready for Prime Time? (Electronic Design Magazine) 8/16/2007 |
| IC Design at Advanced Process Nodes: Add Flex to Your Flow (EDN Magazine) 8/16/2007 |
| Verification Methodologies Keep Pace with Complex IP (EDA DesignLine) 8/14/2007 |
| Embedded Developers Should Embrace FPGAs (EDA DesignLine) 8/9/2007 |
| Making Verification Methodology and Tool Decisions (EDA DesignLine) 8/6/2007 |
| Using Memory Analysis to Create Leaner, Faster, More Reliable Embedded Systems (DSP-FPGA.com) 8/1/2007 |
| Topology Planning and Routing (EDA DesignLine) 7/30/2007 |
| Compiler Optimization for DSP Applications (DSP DesignLine) 7/23/2007 |
| Rethinking the System Design Process (EDA DesignLine) 7/23/2007 |
| Autovectorization for the GCC Compiler (EDN Magazine) 7/19/2007 |
| How to Enable Microsoft Office and Visio for RTL Design (Programmable Logic DesignLine) 7/18/2007 |
| Abstraction Levels and Hardware Design (EDA DesignLine) 7/17/2007 |
| Getting Back to Basics with Planning, Metrics, and Management (EDA DesignLine) 7/13/2007 |
| Accelerating MATLAB Using MEX-files (DSP DesignLine) 7/9/2007 |
| Low Power Design Specification from RTL through GDSII (EDA DesignLine) 7/9/2007 |
| Assertions Improve Productivity for All Development Phases (EDA DesignLine) 7/3/2007 |
| An Automated and Objective Measure of Functional Verification Quality (EDA DesignLine) 6/26/2007 |
| Software-Intensive ASICs/ASSPs Demand Integrated Prototyping Solutions (EDA DesignLine) 6/22/2007 |
| Design for Debugging: The Unspoken Imperative in Chip Design (EDN Magazine) 6/21/2007 |
| Design Constraint Verification and Validation: A New Paradigm (EDA DesignLine) 6/18/2007 |
| Practical Power Network Synthesis for Power-Gating Designs (EDA DesignLine) 6/5/2007 |
| Achieving Certified IP Quality Efficiently (EDA DesignLine) 5/29/2007 |
| In the Eye of the DFM/DFY Storm (EDA DesignLine) 5/25/2007 |
| Small, High-Performance ICs Require Wafer-Level RF Measurements (EDN Magazine) 5/24/2007 |
| Taking a Bite Out of Power: Techniques for Low-Power ASIC Design (EDN Magazine) 5/24/2007 |
| How to Simplify Hardware Prototyping with EXP Modules (Programmable Logic DesignLine) 5/23/2007 |
| Measuring Scan Compression Performance (EDA DesignLine) 5/21/2007 |
| Timing Constraints Generation Technology (EDA DesignLine) 5/17/2007 |
| Signal Integrity Analysis in Wireless SoCs (EDA DesignLine) 5/14/2007 |
| Verifying Configurable Verification Interfaces Using OCP (EDA DesignLine) 5/10/2007 |
| A "How To" Tutorial on Logic Analyzer Basics for Digital Design (Programmable Logic DesignLine) 5/2/2007 |
| The Value of a Complete FPGA Design Flow (FPGA and Programmable Logic Journal) 5/1/2007 |
| We Need a New Approach to Accurately Simulate Large Circuits (EDA DesignLine) 4/30/2007 |
| A Tutorial on Tools, Techniques, and Methodology to Improve FPGA Designer Productivity (Programmable Logic DesignLine) 4/25/2007 |
| Rigorous Automated Verification Yields High Quality Silicon (EDA DesignLine) 4/24/2007 |
| Capturing and Sharing Intellectual Property in PCB Design (EDA DesignLine) 4/19/2007 |
| A Methodology for Front-End Ppower Predictability (EDN Magazine) 4/18/2007 |
| Efficient Computing and Advanced Visualization Accelerates Electronic Design
(EDA DesignLine) 4/12/2007 |
| Practical Approaches to Deployment of SystemVerilog Assertions (EDA DesignLine) 4/3/2007 |
| Efficient Simulation and Validation for Mixed-Signal SOCs (EDN Magazine) 3/29/2007 |
| Pragmatic Adoption of Formal Analysis (EDA DesignLine) 3/29/2007 |
| Signal Integrity Approaches Meet the Multi-Gbps Design Challenge (PlanetAnalog) 3/25/2007 |
| Model-Based Metal Fill Optimizes Planarization and Increases Yield (EDA DesignLine) 3/22/2007 |
| Design for Variability: Design, Process, and Manufacturing Variations in Physical Design (EDA DesignLine) 3/19/2007 |
| Accurate Thermal Analysis of Chip/Package Systems (EDA DesignLine) 3/15/2007 |
| Deterministic Name Generation for Incremental Synthesis (FPGA and Programmable Logic Journal) 3/13/2007 |
| Improve Analog/Mixed-Signal Simulator Analysis Using Real-World, Hardware-Generated Ddata (PlanetAnalog) 3/12/2007 |
| Total Power Optimization in RTL-to-GDSII Implementation Flow (EDA DesignLine) 3/12/2007 |
| A Simple New Approach to Hardware Software Co-Verification (Embedded Systems Design (embedded.com)) 3/11/2007 |
| How to Use Composite Current Source Modeling for Crosstalk Noise Analysis (Embedded Systems Design (embedded.com)) 3/9/2007 |
| Design Preservation with SmartCompile and Xilinx Design Tools (Programmable Logic DesignLine) 3/7/2007 |
| The New Wave in Functional Verification: Algorithmic Testbench Technology (EDA DesignLine) 3/5/2007 |
| Integrating Power Awareness into IC Design (EDA DesignLine) 3/1/2007 |
| How to Use M and Simulink for DSP Control and Datapath Design (Programmable Logic DesignLine) 2/21/2007 |
| FPGA I/O Design Is (also) a PCB Problem (FPGA and Programmable Logic Journal) 2/20/2007 |
| New EDA Tools Improve Low Power Design (EDA DesignLine) 2/19/2007 |
| Mathematical Package Helps in Circuit Design (EDA DesignLine) 2/15/2007 |
| Achieving Completeness in IP Functional Verification (EDA DesignLine) 2/12/2007 |
| Achieving Timing Convergence (EDA DesignLine) 2/8/2007 |
| Generate FPGA Accelerators from C (DSP DesignLine) 2/8/2007 |
| Getting the Most Out of ASIC Prototyping with FPGAs (Programmable Logic DesignLine) 2/7/2007 |
| Getting the Most Out of ASIC Prototyping with FPGAs (Programmable Logic DesignLine) 2/7/2007 |
| Reducing FPGA Compile Time Using Parallel Compilation Methodology (EDA DesignLine) 2/5/2007 |
| Programmable Accelerators: Hardware Performance with Software Flexibility (DSP DesignLine) 2/1/2007 |
| Weapons of Noise Detection (Electronic Design Magazine) 2/1/2007 |
| How to Architect, Design, Implement, and Verify Low-Power Digital ICs (EDA DesignLine) 1/29/2007 |
| How to Design 65-nm FPGA DDR2 Memory Interfaces for Signal Integrity (Programmable Logic DesignLine) 1/24/2007 |
| Test Data Provides Yield Improvement Metrics (EDA DesignLine) 1/22/2007 |
| Beyond Spice: Field-Solver Software Steps in for Modeling High-Frequency, Space-Constrained Circuits (EDN Magazine) 1/18/2007 |
| Gain Abstraction and Accuracy from RTL Power Estimation (Electronic Design Magazine) 1/18/2007 |
| How to Achieve Faster Compile Times in High-Density FPGAs (Programmable Logic DesignLine) 1/17/2007 |
| Defining the TLM-to-RTL Design Flow (EDA DesignLine) 1/15/2007 |
| Achieving 100% Visibility with FPGA-based ASIC Prototypes Running at Real-Time Hardware Speeds (Programmable Logic DesignLine) 1/8/2007 |
| Top 10 Methods for ASIC Power Minimization: Part 1 (Power Management DesignLine) 1/8/2007 |
| Optimize Your DSPs for Power and Performance (DSP DesignLine) 1/4/2007 |
| Timing Is Everything in SOC Design (EDN Magazine) 1/4/2007 |
| User-Friendly Model Simplifies Spice Op-amp Simulation (EDN Magazine) 1/4/2007 |
| Centralized Storage Caching Fixes the EDA Compute Bottleneck (EDA DesignLine) 12/31/2006 |
| Power Exploration in High-Level Synthesis (FPGA and Programmable Logic Journal) 12/19/2006 |
| Practical Applications of Statistical Static Timing Analysis (EDA DesignLine) 12/18/2006 |
| Good Or No Good? An Insider Look at What Works for ESL (Electronic Design Magazine) 12/15/2006 |
| Quickly Find Elusive Signal-Integrity Problems in High-Speed Designs (Electronic Design Magazine) 12/15/2006 |
| PSL Verification Package for the Open Core Protocol (EDA DesignLine) 12/14/2006 |
| Overcoming High-Volume IC Design Challenges to Maximize Profits (EDA DesignLine) 12/11/2006 |
| Globalization in an Analog/Mixed-Signal World (EDA DesignLine) 12/7/2006 |
| Graphical Tools for Rapid Sesign, Prototyping, and Deployment (DSP DesignLine) 12/6/2006 |
| Unified FPGA-ASIC Design Flow Provides Designers Versatility in Meeting Production Goals (FPGA and Programmable Logic Journal) 12/5/2006 |
| Enterprise System Level (ESL) Verification - Part 2 (EDA DesignLine) 12/4/2006 |
| Battling bugs: Embedded Debugging Tactics (EDN Magazine) 12/1/2006 |
| Using Fill Synthesis for Enhanced Planarization - Part 2 (EDA DesignLine) 11/30/2006 |
| Speed Hardware Development with Model-Based Design (DSP DesignLine) 11/24/2006 |
| Low-cost Kits: The New FPGA-Designer Trend (EDN Magazine) 11/23/2006 |
| Modeling Gaps in State-of-the-Art Mixed-Signal SOC Design (EDN Magazine) 11/23/2006 |
| We Need "Enterprise" System-Level Solutions (EDA DesignLine) 11/20/2006 |
| Do's and Don'ts for EM Simulation Success (EDA DesignLine) 11/16/2006 |
| Partial Reluctance Extraction (EDA DesignLine) 11/13/2006 |
| Speed Up Downconverter Implementation with Rapid Prototyping (Wireless Net DesignLine) 11/13/2006 |
| Designing Consumer Electronics: Feeling the Squeeze (EDN Magazine) 11/9/2006 |
| Globalization and Analog (EDN Magazine) 11/9/2006 |
| Why It's Time to Redefine ESL (EDA DesignLine) 11/3/2006 |
| Test Methods Identify Small Delay Defects (EDA DesignLine) 10/30/2006 |
| EDA Tools Platforms Increase Productivity in the Nanometer Era (EDA DesignLine) 10/19/2006 |
| How to Utilize Advanced FPGA Features without Getting Locked into an Architecture (Programmable Logic DesignLine) 10/18/2006 |
| Metrics Measure IC Design Productivity (EDA DesignLine) 10/16/2006 |
| ASIC Design Managers Face Gobal Challenges (EDN Magazine) 10/12/2006 |
| Formal Techniques Solidify Power-Grid Verification (EDN Magazine) 10/12/2006 |
| A Holistic Approach to System-Level Design andVverification Success (EDA DesignLine) 10/9/2006 |
| Does Virtualization Drive the Future? (EDN Magazine) 9/28/2006 |
| Augmenting Your Verification Infrastructure with an External Process (EDA DesignLine) 9/25/2006 |
| Power Integrity Analysis for Billion Transistor Full-Custom Designs (EDA DesignLine) 9/17/2006 |
| Flexible Constraint-Management Drives Next-Generation Mixed-Signal Design (eeDesign (EE Times EDA News)) 9/11/2006 |
| SystemVerilog Reference Verification Methodology: VMM Adoption (eeDesign (EE Times EDA News)) 9/4/2006 |
| An Overview of On-chip Compression Architectures (EDN Magazine) 9/1/2006 |
| Solving the Toughest Problems in CDC Analysis (eeDesign (EE Times EDA News)) 8/28/2006 |
| Integrating PCB and FPGA Constraints (FPGA and Programmable Logic Journal) 8/22/2006 |
| Virtual Prototyping Speeds Mixed-Signal IC Design (eeDesign (EE Times EDA News)) 8/21/2006 |
| Verification Challenges of Embedded Memory Devices (eeDesign (EE Times EDA News)) 8/14/2006 |
| Verification IP Takes a Broader Role (eeDesign (EE Times EDA News)) 8/7/2006 |
| Reducing Cycle Times for Design Rule Checking (eeDesign (EE Times EDA News)) 7/31/2006 |
| Using Statistical Activity for Power Estimation (eeDesign (EE Times EDA News)) 7/24/2006 |
| Magnetic-field Measurements Hold the Key to Reducing DC/DC EMI (EDN Magazine) 7/20/2006 |
| Pulse-Latch Approach Reduces Dynamic Power (eeDesign (EE Times EDA News)) 7/17/2006 |
| Constraint-Driven Physical Design Speeds IC Convergence (eeDesign (EE Times EDA News)) 6/26/2006 |
| On-Chip Variation and Timing Closure (EDN Magazine) 6/22/2006 |
| Core-Aassisted Approach Accelerates Debug of FPGA DDR II Interfaces (Programmable Logic DesignLine) 6/21/2006 |
| Sequential Equivalence Checking for RTL Models (eeDesign (EE Times EDA News)) 6/19/2006 |
| A Bridging Model for ESL Synthesis (eeDesign (EE Times EDA News)) 5/29/2006 |
| SystemVerilog Gains a Foothold in Verification (Electronic Design Magazine) 5/25/2006 |
| How Assertions Can Be Used for Design (eeDesign (EE Times EDA News)) 5/22/2006 |
| How to Adopt Assertion-Based Verification (ABV) into Standard Design Flows (Programmable Logic DesignLine) 5/8/2006 |
| System-Level Design Language Arrives (Electronic Engineering Times (EE Times)) 5/8/2006 |
| SystemVerilog Reference Verification Methodology: RTL (eeDesign (EE Times EDA News)) 5/1/2006 |
| Keys to Simulation Acceleration and Emulation Success (EDN Magazine) 4/27/2006 |
| Temperature-Aware Design for Mixed-Signal ICs (eeDesign (EE Times EDA News)) 4/24/2006 |
| Design High-Speed Data Links with Link-Level Simulation (Electronic Design Magazine) 4/13/2006 |
| Using Complex Triggers in an FPGA-Based RTL Debugger (Programmable Logic DesignLine) 4/12/2006 |
| SystemVerilog Reference Verification Methodology: Introduction (eeDesign (EE Times EDA News)) 3/27/2006 |
| Are You Designing with Too Many Significant Figures? (FPGA and Programmable Logic Journal) 3/21/2006 |
| Facing the Challenges in Analog Design (eeDesign (EE Times EDA News)) 3/13/2006 |
| Increasing Visibility in FPGA Prototypes and Emulators (Programmable Logic DesignLine) 3/7/2006 |
| How to Achieve Fast Timing Closure on FPGA Designs (Programmable Logic DesignLine) 3/1/2006 |
| Preview USB Performance in an SOC Design Using a SystemC Virtual Platform (EDN Magazine) 2/16/2006 |
| Scopes: More than Meets the Eye (EDN Magazine) 2/16/2006 |
| Spring "Board" To FPGA Design Success (Electronic Design Magazine) 2/16/2006 |
| Compiling FPGA Netlists for Formal Verification (eeDesign (EE Times EDA News)) 2/6/2006 |
| Dual Threshold Voltages and Power-Gating Design Flows Offer Good Results (EDN Magazine) 2/2/2006 |
| It's Evolution, Not Revolution, for PCB Tools (Electronic Design Magazine) 2/2/2006 |
| Chip Assembly Challenges and Solutions (eeDesign (EE Times EDA News)) 1/23/2006 |
| Rail-Signoff Analysis Ensures SoC Power Integrity (Electronic Design Magazine) 1/19/2006 |
| How to Choose Custom IC Design Tools (eeDesign (EE Times EDA News)) 1/16/2006 |
| Critical Area Optimizations Improve IC Yields (eeDesign (EE Times EDA News)) 1/9/2006 |
| Design Challenges Steer Automotive Electronics (EDN Magazine) 1/5/2006 |
| High-Speed PCB Design: Symmetry and Spinoffs (eeDesign (EE Times EDA News)) 1/2/2006 |
| An Introduction to Symbolic Simulation (eeDesign (EE Times EDA News)) 12/19/2005 |
| Using SystemVerilog for Functional Verification (eeDesign (EE Times EDA News)) 12/5/2005 |
| The Case for Hardware/Software Co-Verification (FPGA and Programmable Logic Journal) 11/8/2005 |
| Tackling Test Challenges for Low-Power Design (eeDesign (EE Times EDA News)) 11/7/2005 |
| Managing Variations in IC Physical Design (eeDesign (EE Times EDA News)) 10/24/2005 |
| Test Takes New Role in Yield Improvement (eeDesign (EE Times EDA News)) 10/17/2005 |
| Verification Moves to a Higher Level (eeDesign (EE Times EDA News)) 10/3/2005 |
| The History and Future of Scan Design (eeDesign (EE Times EDA News)) 9/19/2005 |
| It’s Not All About the FPGA Anymore (FPGA and Programmable Logic Journal) 9/15/2005 |
| Thermal Integrity: A Must for Low-Power IC Digital Design (EDN Magazine) 9/15/2005 |
| Multiprocessing Speeds IC Physical Verification (eeDesign (EE Times EDA News)) 9/12/2005 |
| Designing ICs with the "X" Architecture (eeDesign (EE Times EDA News)) 8/29/2005 |
| Easing Verification Challenges for IP Reuse (eeDesign (EE Times EDA News)) 8/22/2005 |
| Synthesis Attacks the Abstract (Electronic Design Magazine) 8/18/2005 |
| Who Are You Buying Your EDA Software From? (EDN Magazine) 8/18/2005 |
| Advanced Modeling Verifies Backplane Designs (eeDesign (EE Times EDA News)) 8/15/2005 |
| Intermediate Verification Model Bridges High and Low Levels of Abstraction
(Chip Design Magazine) 8/1/2005 |
| Shape The Design of Wireless Chips (Chip Design Magazine) 8/1/2005 |
| EDA Can't Afford to Ignore Test Chips Any Longer (Electronic Design Magazine) 7/15/2005 |
| IBIS 4.1 Enhances Signal Integrity Modeling (eeDesign (EE Times EDA News)) 7/4/2005 |
| SoC Designers: Learn the What, Why, and How of Transactions (Electronic Design Magazine) 6/23/2005 |
| Equivalency Checking Verifies Sequential Changes (eeDesign (EE Times EDA News)) 6/20/2005 |
| A Thermal-Aware IC Design Methodology (eeDesign (EE Times EDA News)) 6/13/2005 |
| Top-down Approach Speeds Mixed-Signal design (eeDesign (EE Times EDA News)) 6/6/2005 |
| The "Why" and "What" of Algorithmic Synthesis (eeDesign (EE Times EDA News)) 5/2/2005 |
| Getting the Most Out of Formal Analysis (eeDesign (EE Times EDA News)) 4/25/2005 |
| Model-Based Approach Allows Design for Yield (eeDesign (EE Times EDA News)) 4/18/2005 |
| Ensure Valid Design Constraints Throughout the Design Process (EDN Magazine) 4/14/2005 |
| What Designers Need to Know About TCAD (eeDesign (EE Times EDA News)) 4/4/2005 |
| All Design is Analog -- Some More So than Others (EDN Magazine) 3/31/2005 |
| Getting to a Higher Level (Electronic Design Magazine) 3/31/2005 |
| XML Provides Language for Hardware Specification (Electronic Engineering Times (EE Times)) 3/28/2005 |
| Free Tool Friday: How Good Are FPGA Vendor Tools? (FPGA and Programmable Logic Journal) 3/22/2005 |
| Low-Power Flow Enables Multi-Supply Voltage ICs (Electronic Engineering Times (EE Times)) 3/21/2005 |
| Modeling Gigabit Backplanes from Measurements (EDN Magazine) 3/17/2005 |
| Breathing Life into Hardware and Software Codesign (Embedded Systems Design (embedded.com)) 3/16/2005 |
| A Methodology for IC Power Grid Design (eeDesign (EE Times EDA News)) 3/11/2005 |
| A Methodology for DSP-Based FPGA Design (eeDesign (EE Times EDA News)) 3/9/2005 |
| Plug and Play Design Methodologies for FPGA-based Signal Processing (FPGA and Programmable Logic Journal) 3/8/2005 |
| Design Complexity Requires System-Level Design (EDN Magazine) 3/3/2005 |
| Design FPGA-Based DSPs for Performance and Power (Chip Design Magazine) 3/1/2005 |
| Speed SoC Software with Coprocessor Synthesis (Chip Design Magazine) 3/1/2005 |
| Take Designs from Algorithms to Artwork (Chip Design Magazine) 3/1/2005 |
|
Tutorials, White Papers & Conference Papers on EDA and EDA tools |
| 4.25 GBps Laser Driver: Design Challenges and EDA Tool Limitations (Design Automation Conference (DAC)) |
| A Comparison of Two VHDL Memory Modeling Techniques (Free Model Foundry) |
| A Complete Design Solution for Structured ASICs (Magma Design Automation, Inc.) |
| A Fully-Automated De-Synchronization Flow for Synchronous Circuits (52.3) (Design Automation Conference (DAC)) |
| A Multilevel Technique for Robust and Efficient Extraction of Phase Macromodels of Digitally Controlled Oscillators (Design Automation Conference (DAC)) |
| A Network Security Processor Design Based on an Integrated SOC Design and Test Platform (Design Automation Conference (DAC)) |
| A New LP Based Incremental Timing Driven Placement for High Performance Designs (Design Automation Conference (DAC)) |
| A Parallel Low-Rank Multilevel Matrix Compression Algorithm for Parasitic Extraction of Electrically Large Structures (Design Automation Conference (DAC)) |
| A Reconfigurable Design-for-Debug Infrastructure for SoCs (Design Automation Conference (DAC)) |
| A Robust Envelope Following Method Applicable to Both Non-Autonomous and Oscillatory Circuits (Design Automation Conference (DAC)) |
| Achieving Low Power in 65-nm Cyclone III FPGAs (Altera Corp.) |
| Advanced Virtual Platform Validation Methodology (JEDA Technologies, Inc.) |
| An Analysis Methodology for Dynamic Power Gating (Sequence Design, Inc.) |
| An Effective Guidance Strategy for Abstraction-Guided Simulation (5.1) (Design Automation Conference (DAC)) |
| An Efficient and Versatile Scheduling Algorithm Based on SDC Formulation (Design Automation Conference (DAC)) |
| An Introduction to HDLs for Simulation and Synthesis (Accolade Design Automation) |
| An Introductory VHDL Tutorial (Green Mountain Computing Systems, Inc.) |
| Area Constraint Evaluation for FPGAs (Synplicity, Inc.) |
| ASIC Design Flow Tutorial (Hacettepe University) |
| ASIC Verification in Transition: How to Get the Most Out of FPGA Prototyping! (Synplicity, Inc.) |
| Assertion Based Verification, ESL to Gate (JEDA Technologies, Inc.) |
| Assertion-Based Verification: Choosing the Right Solution (Atrenta, Inc.) |
| Automatic Formal Verification of Fused-Multiply-Add FPUs (IBM Corp.) |
| Automatic Invariant Strengthening to Prove Properties in Bounded Model Checking (Design Automation Conference (DAC)) |
| Automating Analog Verification in a Mixed-Mode Simulation (asicNorth) |
| Automating Sequential Clock Gating (Calypto Design Systems, Inc.) |
| Boundary Scan Tutorial (ASSET InterTech, Inc.) |
| Boundary Scan Tutorial (Corelis, Inc.) |
| Chill: A New Approach to Power Analysis (Envis Corp.) |
| Chip & Board Testability Assessment Checklist (ASSET InterTech, Inc.) |
| Clock Buffer and Wire Sizing Using Sequential Programming (Design Automation Conference (DAC)) |
| Clock Concurrent Optimization (Azuro, Inc.) |
| Coding Guidelines for Datapath Synthesis (Synopsys, Inc.) |
| Combining Impulse C with uClinux for MicroBlaze-based FPGAs (Impulse Accelerated Technologies, Inc.) |
| Combining Structural and Functional Verification Techniques to Improve Effective CDC Verification (Atrenta, Inc.) |
| Computer-Aided Architecture Design and Optimized Implementation of Distributed Automotive EE Systems (31.4) (Design Automation Conference (DAC)) |
| Concurrent Verification: Resolving Conflicting Goals (Synterix Technology) |
| Constraint-Driven Floorplan Repair (Design Automation Conference (DAC)) |
| Coverage Manager Methodology Accelerates Complex SOC Verification (Ingot Systems, Inc.) |
| Debugging Today's Complex Analog Designs Requires Much More than Waveform Analysis (Sandwork Design, Inc.) |
| Delivering Synthesizable Verification IP for Test Benches (Bluespec, Inc.) |
| Deploying Properties Assertions and Coverage (Aldec, Inc.) |
| Design in Reliability for Communication Designs (Design Automation Conference (DAC)) |
| Design Tools for Reliability Analysis (Design Automation Conference (DAC)) |
| Design Verification Methodology Aldec DO-254 Compliance Tool Set (Aldec, Inc.) |
| Designer's Guide to Verilog (Doulos) |
| Does ESL Really Need to Be That Hard to Use? (JEDA Technologies, Inc.) |
| Early Chip Sizing Carries High Financial and Technical Implications (Toshiba America Electronic Components, Inc. (TAEC)) |
| Early Cutpoint Insertion for High-Level Software vs. RTL Formal Combinational Equivalence Verification (Design Automation Conference (DAC)) |
| Effcient Symbolic Simulation via Dynamic Scheduling, Don't Caring, and Case Splitting (IBM Corp.) |
| Efficient Signal and Power Integrity Analysis Using Parallel Techniques (Sigrity, Inc.) |
| Electronic System-Level Development: Finding the Right Mix of Solutions for the Right Mix of Engineers (Byte Paradigm) |
| Electronic Systems Prototyping: Tools and Methodologies for Better Observability (Byte Paradigm) |
| Electronics: The New Differential in the Automotive Industry (26.1) (Design Automation Conference (DAC)) |
| EMI Reduction and PCB Layout Techniques (TLSI, Inc.) |
| Emulation: Enabling It on Every Desktop (Bluespec, Inc.) |
| Enabling Assertion-Based Verification (Zocalo Tech, Inc.) |
| Enabling Large-Scale Pervasive Logic Verification through Multi-Algorithmic Formal Reasoning (IBM Corp.) |
| Escape Routing for Dense Pin Clusters in Integrated Circuits (4.2) (Design Automation Conference (DAC)) |
| Evita Interactive VHDL Tutorial (Aldec, Inc.) |
| Evita Verilog Interactive Tutorial (Aldec, Inc.) |
| Exploiting Constraints in Transformation-Based Verification (IBM Corp.) |
| Exploiting Suspected Redundancy without Proving It (IBM Corp.) |
| Fast Falsification Based on Symbolic Bounded Property Checking (Design Automation Conference (DAC)) |
| Fast, Efficient RTL Debug for Programmable Logic Designs (Synplicity, Inc.) |
| Fault Detection and Diagnosis with Parity Trees for Space Compaction of Test Responses (Design Automation Conference (DAC)) |
| Fine-Grained Sleep Transistor Sizing Algorithm for Leakage Power Minimization (6.1) (Design Automation Conference (DAC)) |
| FPGA-based Prototyping: Why All ASICs Should be Prototyped Using FPGAs (Synplicity, Inc.) |
| Free Models: What Are They? How Are They Used? How Can They Be Free? (Free Model Foundry) |
| Getting Started with Requirements-Based Verification (Verilab, Ltd.) |
| Global Design Data Management Report 2010 (IC Manage, Inc.) |
| Global Design Management Report 2009 (IC Manage, Inc.) |
| Guidelines for Chip DFT Based on Boundary Scan or JTAG (ASSET InterTech, Inc.) |
| High Performance Scalable Hardware Configuration Management (IC Manage, Inc.) |
| High-Level "Plug-and-Play" Specification, Modeling and Synthesis of Pipelined Architectures with Bluespec’s PAClib (Bluespec, Inc.) |
| High-Speed I/O Design Considerations in Low-Cost Packaging Applications (Toshiba America Electronic Components, Inc. (TAEC)) |
| How to Minimize Energy Consumption While Maximizing ASIC and SOC Performance (Tensilica, Inc.) |
| Impact of Multiple-Voltage Domain Design Implementation on Large, Complex SoCs (Toshiba America Electronic Components, Inc. (TAEC)) |
| Introduction to Verilog (verilog.com) |
| Introduction to VHDL (electrosofts.com) |
| IP Exchange: I'll Show You Mine if You'll Show Me Yours (53.1) (Design Automation Conference (DAC)) |
| IP Solutions for Synchronizing Signals that Cross Clock Domains (Synopsys, Inc.) |
| IPR: An Integrated Placement and Routing Algorithm (4.4) (Design Automation Conference (DAC)) |
| JTAG Guidelines for Board DFT: Part 1 (ASSET InterTech, Inc.) |
| JTAG Guidelines for Board DFT: Part 2 (ASSET InterTech, Inc.) |
| Kelvin: A New Approach to Power Analysis (Envis Corp.) |
| Language Extensions to SystemC: Process Control Constructs (3.3) (Design Automation Conference (DAC)) |
| Leveraging Semi-Formal and Sequential Equivalence Techniques for Multimedia SoC Performance Validation (5.2) (Design Automation Conference (DAC)) |
| Leveraging System Models for RTL Functional Verification Using Sequential Logic Equivalence Checking (Calypto Design Systems, Inc.) |
| Logical Hardware debuggers for FPGA-based Systems (BYU Configurable Computing Lab) |
| Lookup Table Based Simulation and Statistical Modeling of Sigma-Delta ADCs (Design Automation Conference (DAC)) |
| Megatrends and EDA 2017 (2.1) (Design Automation Conference (DAC)) |
| MFG Interface: Making Manufacturing Work for You (7.1) (Design Automation Conference (DAC)) |
| Mixed-Signal IC Design (University of Colorado at Boulder) |
| Model-Driven Validation of SystemC Designs (3.2) (Design Automation Conference (DAC)) |
| Modeling and Estimation of Full-Chip Leakage Current Considering Within-Die Correlation (6.3) (Design Automation Conference (DAC)) |
| Modeling OCP Interfaces in SystemC: Standards built on top of OSCI’s TLM-2 (OCP International Partnership (OCP-IP)) |
| Multimedia Application Specific Engine Design Using High Level Synthesis (Synfora, Inc.) |
| Multiple-Detect ATPG Based on Physical Neighborhood (Design Automation Conference (DAC)) |
| Navigating the System to RTL Continuum (Calypto Design Systems, Inc.) |
| NSCa and PSL: Why Native Assertion Is Iportant in SystemC? (JEDA Technologies, Inc.) |
| OCP TLM for Architectural Modeling (CoWare, Inc.) |
| Optimal Cell Flipping in Placement and Floorplanning (Design Automation Conference (DAC)) |
| OSCI TLM2.0 Standard Compliance: Why Bother? (JEDA Technologies, Inc.) |
| Overcoming the Challenges of Design Verification and Hardware Validation (Kozio, Inc.) |
| PANEL: Building a Verification Test Plan: Trading Brute Force for Finesse (Design Automation Conference (DAC)) |
| PANEL: DFM: Where's the Proof of Value? (Design Automation Conference (DAC)) |
| PANEL: The IC Nanometer Race – What Will It Take to Win? (Design Automation Conference (DAC)) |
| PANEL: Tomorrow's Analog: Just Dead or Just Different (Design Automation Conference (DAC)) |
| PANEL: Variation-Aware Analysis: Savior of the Nanometer Era? (Design Automation Conference (DAC)) |
| Perl for Hardware Designers (Doulos) |
| Power Management Poses a Critical Design Constraint in Consumer Applications (Toshiba America Electronic Components, Inc. (TAEC)) |
| Power-Saving Clock-Gating Technique is an Inseparable Part of SoC Design (Toshiba America Electronic Components, Inc. (TAEC)) |
| Pragmatic Simulation-Based Verification of Clock Domain Crossing Signals and Jitter Using SystemVerilog Assertions (Verilab, Ltd.) |
| Reconfiguration for Reliability Tools (Synplicity, Inc.) |
| Reducing AMBA-based SoC Design Time by More Than 50% Using coreAssembler (Synopsys, Inc.) |
| Scalable Automated Verification via Expert-System Guided Transformations (IBM Corp.) |
| Scalable Compositional Minimization via Static Analysis (IBM Corp.) |
| Scalable Sequential Equivalence Checking Across Arbitrary Design Transformations (IBM Corp.) |
| Scheduling-based Test-case Generation for Verification of Multimedia SoCs (Design Automation Conference (DAC)) |
| Semiconductor IC Test and Design-for-Test Fundamentals (Inovys Corp.) |
| Sequential Equivalence Checking: A New Approach to Functional Verification of Datapath and Control Logic Changes (Calypto Design Systems, Inc.) |
| Shorten and Simplify SoC Verification using a Generic eVC (Verilab, Ltd.) |
| Si2 Power Aware Design Flows (Silicon Integration Initiative, Inc. (Si2)) |
| Si2 Power Reduction Stimulus and Low Power Design Techniques (Silicon Integration Initiative, Inc. (Si2)) |
| Silicon Design Chain Extends Low Power Design Collaboration (Cadence Design Systems, Inc.) |
| Simulink-Based MPSoC Design Flow: Case Study of Motion-JPEG and H.264 (3.4) (Design Automation Conference (DAC)) |
| Solutions for SPI Protocol Testing and Debugging in Embedded System (Byte Paradigm) |
| Structured and Platform ASIC Architectures Mandate Custom Physical Synthesis Solutions (Synplicity, Inc.) |
| Successfully Designing FPGA-Based Systems (Cadence Design Systems, Inc.) |
| Synthesizable Models Enable Early Emulation for Complex IP (Bluespec, Inc.) |
| Synthesizing SVA Local Variables for Formal Verification (5.3) (Design Automation Conference (DAC)) |
| System Level Design and Verification Using a Synchronous Language (Formal Sciences, Inc.) |
| System Level Design: SystemC Using Transaction Level Modeling (Aldec, Inc.) |
| Systematic Development of Nonlinear Analog Circuit Macromodels through Successive Operator Composition and Nonlinear Model Decoupling (Design Automation Conference (DAC)) |
| SystemC Training Course (Forte Design Systems, Inc.) |
| SystemC Tutorial (ASIC World) |
| SystemC: An Introduction for Beginners (electrosofts.com) |
| SystemVerilog Implicit Port Connections: Simulation and Synthesis (Sunburst Design, Inc.) |
| SystemVerilog Tutorial (ASIC World) |
| SystemVerilog Tutortial (electrosofts.com) |
| Test Response Compactor with Programmable Selector (Design Automation Conference (DAC)) |
| The DFM Pandemic: How Many Chips Have to Die? (Pyxis Technology, Inc.) |
| The Embedded Path to Low Defects per Million and Fast Silicon Bring-Up (LogicVision, Inc.) |
| The Myth of SystemVerilog Interoperability (Verilab, Ltd.) |
| The Open Verification Methodology (OVM), (OVM World) |
| The Power of RTL Clock Gating (Calypto Design Systems, Inc.) |
| The System-on-Chip Integration Challenge: The Need for Design-for-Debug Tools and Technologies (DAFCA, Inc.) |
| TLM-2.0 in Action: An Example-based Approach to Transaction-Level Modeling and Model Interoperability (Open SystemC Initiative (OSCI)) |
| Towards a C++-Based Design Methodology Facilitating Sequential Equivalence Checking (Design Automation Conference (DAC)) |
| TROY: Track Router with Yield-driven Wire Planning (4.3) (Design Automation Conference (DAC)) |
| Unified Functional Verification Approach for GPON SoC Application (Synterix Technology) |
| Unified TLM 2.0 Coverage Measurement (JEDA Technologies, Inc.) |
| Unknown-Tolerance Analysis and Test-Quality Control for Test Response Compaction Using Space Compactors (Design Automation Conference (DAC)) |
| Use of C/C++ Models for Architecture Exploration and Verification of DSPs (Design Automation Conference (DAC)) |
| Using FPGA-Based Simulation Acceleration In a Typical ASIC Design Flow (Aldec, Inc.) |
| Using Impulse C with BlueCat Linux 5.4.2 on MicroBlaze via FSL (Impulse Accelerated Technologies, Inc.) |
| Using Program Specialization to Speed SystemC Fixed-Point Simulation (Formal Sciences, Inc.) |
| Using SystemVerilog Assertions for Functional Coverage (Verilab, Ltd.) |
| Using SystemVerilog Assertions in Gate-Level Verification Environments (Verilab, Ltd.) |
| Utilizing Clock-Gating Efficiency to Reduce Power in RTL Designs (Calypto Design Systems, Inc.) |
| VERA Verification Tutorial (ASIC World) |
| Verification Coverage: When is Enough Enough? (41.1) (Design Automation Conference (DAC)) |
| Verification without Testbenches (Calypto Design Systems, Inc.) |
| Verilog HDL Quick Reference Guide
(Sutherland HDL, Inc.) |
| Verilog Tutorial (Yankee Bush Software) |
| Verilog Tutorial (University of Maryland (ECE)) |
| VHDL Language Guide (Accolade Design Automation) |
| VHDL Tutorial (Yankee Bush Software) |
| VHDL Tutorial (University of Erlangen-Nürnberg) |
| VHDL Tutorial (ASIC World) |
| VHDL Verification Course (Stefan Doll) |
| Virtual Platforms for Software Development (CoWare, Inc.) |
| Visibility Enhancement for Silicon Debug (Design Automation Conference (DAC)) |
| We Haven’t Survived 65nm: We’re Just in the Eye of the Storm! (Pyxis Technology, Inc.) |
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