| Magazine & Journal Articles Online |
Featured Online Articles
Reusability, Usability and FlexibilityMindTree, Ltd.
in Programmable Logic DesignLineAugust 18, 2010 -- Discussions on reusability and reusable components are widespread among the practitioners of software engineering as well as the academia. A library of reusable components, one among the strategic engineering assets of any successful IT organization contributes not only to productivity improvements but also to product quality throughout the life cycle of any software product. . . . read more IP Integration: Is It the Real System-Level Design?EDN MagazineAugust 12, 2010 -- The search for productivity in SOC (system-on-chip) design is a search for balance between abstraction and automation. Greater abstraction at a step in the design flow means fewer design elements to process. Greater automation means that each element requires less human attention. Ideally, designers could capture an abstract representation of an SOC's intended behavior, verify that the representation describes the desired chip, and push a button to tape-out. We are not yet there. . . . read more Reduce Embedded SOC Design Cost and Optimize IP IntegrationCadence Design Systems, Inc.
in Embedded Systems Design (embedded.com)August 9, 2010 -- In the past, most of the design effort in an SOC was centered on creating unique new logic that differentiated the design from other designs available. It has been this understanding of SoC design that drove the evolution of design tools and technologies over the past decade – the focus on new logic creation. Fast-forward to today and we find a very different situation, with SOCs that contain large amounts of internal and third-party intellectual property (IP) integrated into complex systems. . . . read more Using In-Design Physical Verification to Reduce Tape-Out SchedulesSynopsys, Inc.
in Design & ReuseAugust 2, 2010 -- Physical designers moving to lower foundry nodes worry about how to verify and deliver a design that is free of DRC violations while meeting their tape-out schedule. This can be quite challenging given that the number and complexity of DRC rules is increasing and designs are getting bigger. The need for a better understanding of the manufacturing issues during the design phase raises concerns about how to best address these issues. . . . read more
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Publications make a wealth of articles about SOC design, EDA tools, intellectual property, ASICs, and programmable logic available online. To save you surfing time, SOCcentral.com regularly scans the leading print and online publications for the most relevant technology, product and industry articles – then abstracts and links to them.
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Articles published online since Sunday, July 11, 2010 (last 60 days) | | Reusable Device Simulation Models for Embedded System Virtual Platforms (Mentor Graphics Corp. ) in Design & Reuse (8/24/2010) | | SystemVerilog Configurable Coverage Model In an OVM setup: Concept of Reusability (AppliedMicro (AMCC) ) in EDA DesignLine (8/24/2010) | | Harness Speed, Performance, Signal Integrity, and Low-Current Advantages of 65-nm QDR SRAMs (Cypress Semiconductor Corp. ) in Communications DesignLine (8/23/2010) | | Dual-Core Architectures In Automotive SoCs (Freescale Semiconductor, Inc. ) in Automotive DesignLine (8/23/2010) | | Using Switched Capacitors to Create Programmable Analog Logic Blocks In Mixed-Signal Designs (Cypress Semiconductor Corp. ) in Programmable Logic DesignLine (8/18/2010) | | Reusability, Usability and Flexibility (MindTree, Ltd. ) in Programmable Logic DesignLine (8/18/2010) | | IP Integration: Is It the Real System-Level Design? in EDN Magazine (8/16/2010) | | Data Storage Yields Increased Design Productivity in EDN Magazine (8/16/2010) | | Packaging Options Expand In RF Power (RF DesignLine ) in Microwave & RF DesignLine (8/16/2010) | | Applying Bayesian Belief Networks to Fault Tree Analysis of Safety-Critical Software (QNX Software Systems, Ltd. ) in Embedded Systems Design (embedded.com) (8/16/2010) | | Reduce Embedded SOC Design Cost and Optimize IP Integration (Cadence Design Systems, Inc. ) in Embedded Systems Design (embedded.com) (8/16/2010) | | Picking the Right Built-In Self-test Strategy for Your Embedded ASIC (Freescale Semiconductor, Inc. ) in Embedded Systems Design (embedded.com) (8/16/2010) | | Transaction Analysis and Debug Across Language Boundaries and Between Abstraction Levels (Mentor Graphics Corp. ) in Design & Reuse (8/16/2010) | | FPGA Compilation On-Site or In the Cloud (National Instruments Corp. ) in Programmable Logic DesignLine (8/16/2010) | | Comparing AMBA AHB to AXI Bus Using System Modeling (Mirabilis Design, Inc. ) in Design & Reuse (8/16/2010) | | An Efficient ASIP Design Methodology in Design & Reuse (8/16/2010) | | Using In-Design Physical Verification to Reduce Tape-Out Schedules (Synopsys, Inc. ) in Design & Reuse (8/2/2010) | | Use XML to Build ASIC or SOC Design Specifications (SiBEAM, Inc. ) in Embedded Systems Design (embedded.com) (7/31/2010) | | ESL Synthesis: Tips for Implementing a Viable ESL-Synthesis Flow (Gary Smith EDA ) in EDN Magazine (7/30/2010) | | Protect Your goal with Post-Silicon Formal Verification (Jasper Design Automation ) in Design & Reuse (7/30/2010) | | EM Simulation for EMC: Keeping a Lid on Interference in EDN Magazine (7/30/2010) | | Design Quality and Its Impact On Design Closure (Atrenta, Inc. ) in EDN Magazine (7/30/2010) | | IP Re-Engineering and Design Methodology (MindTree, Ltd. ) in Design & Reuse (7/29/2010) | | Accelerating the Time to IC Layout (EDA Solutions, Ltd. ) in EDA DesignLine (7/29/2010) | | Generating AMD Microcode Stimuli Using VCS Constraint Solver (Synopsys, Inc. ) in Design & Reuse (7/29/2010) | | Customized FPGA board for ASIC Prototyping: A Novel Approach with Pre-designed Blocks and Modular FPGA ( ) in Design & Reuse (7/29/2010) | | Embedded Systems Power Down in EDN Magazine (7/29/2010) | | Interoperable DRC/LVS Language Standard Accelerates Physical Verification Turnaround Time for Advanced Nodes (TSMC (Taiwan Semiconductor Manufacturing Company) ) in EDN Magazine (7/27/2010) | | Real-Time Non-intrusive Debugging Framework (Infineon Technologies Corp. ) in Design & Reuse (7/23/2010) | | Give the People What They Want: HLS for RTL Verification (Mentor Graphics Corp. ) in EDA DesignLine (7/21/2010) | |
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Seeing Is Believing: How Visualization Simplifies IC DRC
Michael White
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Verification Challenges
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Dr. Pranav Ashar
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