Featured Online Articles
Boost DFT Efficiency for Large SOCsMentor Graphics Corp.
in Test & Measurement WorldApril 23, 2013 -- One significant design challenge for today's SOCs is managing the impact of the very large design size on EDA tools and flows. Front-end and back-end design flows have managed this challenge by breaking up the design along hierarchical boundaries. The resulting physical cores are then assembled together at the SOC level. This core-based approach to design not only allows EDA tools to run more efficiently but enables multiple design blocks to be completed in parallel, thereby improving overall throughput. The same principles and resulting benefits can be applied towards the design-for-test (DFT) effort as well. . . . read more Demystifying the PLLCypress Semiconductor Corp.
in EDN MagazineApril 1, 2013 -- The phase-locked loop (PLL) is an indispensible component in modern electronic systems. Its function is to generate an accurate output signal of frequency equal to, or a multiple of, the input signal frequency. It is mainly used in modulators/ demodulators and in clock generation/ multiplication. However, when designing a digital communications system on a mixed-signal chip, digital designers tend to avoid PLLs because of their inherent analog nature, and analog designers stay away from them because IDEs involve coding. This article presents a different way of designing a simple PLL. . . . read more Communication-Centric Test and Debug Infrastructure for Multicore SOCsNXP Semiconductors
in Design & ReuseMarch 28, 2013 -- A communication-centric SOC-debug approach using control transactions, as an extension of the traditional, processor-based debug access and control is presented in this article. A structured approach is presented to control both the processor core and other critical hardware units in a hardware-synchronized manner, thereby enabling both synchronous stop and start during a debug session. An efficient and processor independent mechanism to have explicit control the system at run time is presented. The presentation also describes an efficient way to control the system through a tester/ATE. . . . read more Introduction to OpenVG for Embedded 2D Graphics ApplicationsFreescale Semiconductor, Inc.
in Embedded.comMarch 27, 2013 -- OpenVG is an API designed for hardware-accelerated 2D vector graphics. It was designed to help manufacturers create more attractive user interfaces by off-loading computationally intensive graphics processing from the CPU onto a GPU to save energy. It is being used across many platforms, including a number of embedded applications. In this article we will describe the basic capabilities of the OpenVG spec and how to use it in automotive infotainment and instrument display applications. . . . read more
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Articles published online since Saturday, March 30, 2013 (last 8 weeks) |
| A Generic DDR Behavioural Model (eInfochips, Ltd. ) in Design & Reuse (5/22/2013) |
| Leveraging PCIe SSD Performance with a Full Hardware NVMe (IP-Maker ) in Chip Estimate Corp. (5/21/2013) |
| Address Jitter and Noise More Effectively with DDR4 - Part 1 (Agilent Technologies, Inc. ) in EE Times Memory Designline (5/21/2013) |
| Automated ECO Flow for Overall Cycle-Time Reduction (Freescale Semiconductor, Inc. ) in Design & Reuse (5/17/2013) |
| Building an RTL Sign-off Flow (Real Intent, Inc. ) in Tech Design Forum (5/14/2013) |
| Power Verification Is Just as Important as Functional Verification for Complex SOCs (Mentor Graphics Corp. ) in New Electronics Magazine (5/14/2013) |
| Customizing SRAM Content to Obtain Truly Differentiated Products (eSilicon Corp. ) in Chip Estimate Corp. (5/14/2013) |
| Moving to SystemC TLM for Design and Verification of Digital Hardware (Cadence Design Systems, Inc. ) in EE Times EDA Designline (5/13/2013) |
| Understanding On-Board Flash Programming (Micron Technology, Inc. ) in Electronic Design Magazine (5/10/2013) |
| Embedded Devices Gird Up Against Cyber Threats in Electronic Design Magazine (5/9/2013) |
| Eight Requirements for 3D-IC Design (Cadence Design Systems, Inc. ) in Tech Design Forum (5/8/2013) |
| Design Planning for Large SOC Implementation at 40nm: Guaranteeing Predictable Schedule and First-Pass Silicon Success (Open-Silicon, Inc. ) in EDN Magazine (5/7/2013) |
| How to Generate Test Patterns to Detect FinFET Defects (Mentor Graphics Corp. ) in Test & Measurement World (5/6/2013) |
| Design for Manufacturing and Yield in EDN Magazine (5/6/2013) |
| Synthesis-Aware Clock Analysis and Constraints Generation (ICScape, Inc. ) in EE Times EDA Designline (5/6/2013) |
| Physical Verification of finFET and FD-SOI Devices (Synopsys, Inc. ) in Tech Design Forum (5/2/2013) |
| The Power of Developing Hardware and Software in Parallel (Synopsys, Inc. ) in Design & Reuse (5/2/2013) |
| Target Impedance-Based Solutions for Power-Distribution Networks May Not Provide Realistic Assessment in EDN Magazine (5/1/2013) |
| Tracking Down Interference in Complex RF Environments (Agilent Technologies, Inc. ) in EE Times Militray & Aerospace Highlights (4/30/2013) |
| Integrating Sensors into Mobile Devices (Sensor Platforms, Inc. ) in ECN Magazine (4/30/2013) |
| How Small Vendors Compete on Analog IC Market in EE Times Test & Measurement Designline (4/29/2013) |
| Simulation Shows How Real Op Amps Can Drive Capacitive Loads (Maxim Integrated Products, Inc. ) in EDN Magazine (4/28/2013) |
| The Use of FinFETs in IP Design (Synopsys, Inc. ) in Chip Estimate Corp. (4/23/2013) |
| Using Audio Codec IP as the Digital Audio Hub in Mobile Multimedia Systems (Synopsys, Inc. ) in EDN Magazine (4/23/2013) |
| Boost DFT Efficiency for Large SOCs (Mentor Graphics Corp. ) in Test & Measurement World (4/23/2013) |
| FinFET Challenges and Solutions: Custom, Digital, and Sign-Off (Cadence Design Systems, Inc. ) in EE Times EDA Designline (4/22/2013) |
| The Five Key Challenges of 20-nm Custom and Analog Design (Cadence Design Systems, Inc. ) in Tech Design Forum (4/22/2013) |
| Why Flash Storage Needs MEMS (Discera, Inc. ) in EE Times Memory Designline (4/20/2013) |
| Grasp the Critical Issues for a Functioning JESD204B Interface (Analog Devices, Inc. (ADI) ) in EE Times Programmable Logic Designline (4/19/2013) |
| FPGAs Offer Cost-Effective, Flexible Solutions for Remote Radio Heads (Xilinx, Inc. ) in EE Times Programmable Logic Designline (4/18/2013) |
| 3D-IC Integration: A Stepwise Approach (Synopsys, Inc. ) in Tech Design Forum (4/17/2013) |
| Dynamic Microcontroller Reconfiguration Delivers More than 100% Resource Utilization (Cypress Semiconductor Corp. ) in Electronic Design Magazine (4/17/2013) |
| Reducing Energy Consumption in ICT Applications Using the Dynamic Bus Voltage Architecture (Ericsson ) in EDN Magazine (4/17/2013) |
| Complex Standards Demand New Approaches to IP Quality (Arasan Chip Systems, Inc. ) in Chip Estimate Corp. (4/16/2013) |
| The Gesture Interface: A Compelling Competitive Advantage in the Technology Race (Embedded Vision Alliance ) in EE Times Communications Designline (4/16/2013) |
| Stitch and Ship No Longer Viable (Breker Verification Systems, Inc. ) in EE Times EDA Designline (4/15/2013) |
| System Test Using JTAG (eInfochips, Ltd. ) in Design & Reuse (4/15/2013) |
| Small-Signal Simulation in the s-plane (Dolphin Integration ) in EDN Magazine (4/15/2013) |
| Increased Functional Safety Is a Must Have in Networked Embedded Designs (Microsemi SoC Products Group ) in EE Times Programmable Logic Designline (4/11/2013) |
| SOC FPGAs Combine Performance and Flexibility (Altera Corp. ) in EDN Magazine (4/10/2013) |
| Time to Take Up the 3D-Integration Challenge (Synopsys, Inc. ) in Tech Design Forum (4/10/2013) |
| Advances in EDA Design Methodologies Led by Next-Generation FPGAs in DSP-FPGA (4/10/2013) |
| Small-Scale Programmable Logic Devices Offer Numerous Benefits in New Electronics Magazine (4/9/2013) |
| SSM Policy-Driven System Management Updates SOC Architecture to Meet Today's Operation Complexities (ChipStart ) in Chip Estimate Corp. (4/9/2013) |
| Aggressively Combat Noise in Capacitive Touch Applications (Cypress Semiconductor Corp. ) in EDN Magazine (4/8/2013) |
| A Low-Risk, High-Reward Approach to Adopting Formal Methods (STMicroelectronics ) in EE Times EDA Designline (4/8/2013) |
| Developing Power-Sensitive, Low-Current MCU Designs (Silicon Laboratories, Inc. ) in EE Times Power Management Designline (4/4/2013) |
| Building Your UVM Verification Environment for Cache-Coherent Interconnects (Cadence Design Systems, Inc. ) in Design & Reuse (4/4/2013) |
| Extreme Code Density: Energy Savings and Methods (CAST, Inc. ) in Chip Estimate Corp. (4/2/2013) |
| FPGAs Supercharge Instrument Flexibility in EE Times Programmable Logic Designline (4/1/2013) |
| Reclaiming Lost Yield Through Methodical Power-Integrity Optimization (Teklatech ) in EE Times EDA Designline (4/1/2013) |
| Demystifying the PLL (Cypress Semiconductor Corp. ) in EDN Magazine (4/1/2013) |
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