March 13, 2012 -- Blue Pearl Software, Inc. has announced that its Blue Pearl Software Suite, for Windows and Linux operating systems, supports Synopsys' Synplify Pro FPGA synthesis software for VHDL and SystemVerilog designs.

Blue Pearl Software Suite's connection to Synplify Pro software improves interoperability with Synopsys' synthesis flow and makes it easier for FPGA designers to add Blue Pearl Software's automatic Synopsys Design Constraints (SDC) generation to their flows. It offers users improved constraint analysis and a solution that minimizes design risks.

"Our collaboration with Synopsys resulted in an optimized flow that works with Synplify Pro FPGA synthesis software," said Shakeel Jeeawoody, Director of Product Marketing at Blue Pearl. "VHDL and SystemVerilog designers are now able to automatically generate an exhaustive set of constraints that address false and multi-cycle paths and that work with Synopsys' leading synthesis flow."

Blue Pearl Software Suite offers comprehensive RTL analysis, clock-domain crossing (CDC) checks, and automatic Synopsys Design Constraints (SDC) generation for FPGA, ASIC and SOC designs. Its visualization and validation technology gives users immediate feedback for validating automatically generated pre-synthesis longest paths and SDC timing constraints.

Last month, Blue Pearl Software announced Release 6.0 of its Blue Pearl Software Suite with capabilities that support FPGA designers.

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