April 9, 2012 -- Sital Technology, Ltd. has announced that it completed the design of its Enhanced Bit Rate (EBR) 1553 IP core for FPGA. Sital's EBR-1553 IP core is based on Sital's proven 1553 IP cores, with DDC Enhanced Mini-Ace compatible interface. Bus controller, remote terminals and bus monitor IP core configurations are available. The core can work with any FPGA, and requires only a standard RS-485 transceiver which supports 10Mbps.

EBR-1553 is a 10-Mbps bit-rate protocol which utilized the robust Mil-Std-1553 protocol over RS-485 transceivers in a hub-based point-to-point connection. Using network topology of a star between the bus controller and remote terminals enables high-speed and robust data transfer.

Users of Sital's EBR-1553 IP core can select the core configuration (BC, RT, MT), clock frequency, memory configuration and FPGA family. The back-end interface can be targeted to a local-bus, PCI bus or simple FIFO/ registers read/ write bus.

The IP Core is provided with software drivers for Windows, Linux, QNX along with high-level API. The API is fully compatible with DDC API, so that software developers already used to the DDC interface can easily transfer their existing applications to EBR.

An EBR-1553 tester is also available, utilizing the exact same hardware of the commonly used MultiComBox, only with an updated firmware.

Availability