April 10, 2012 -- Oasys Design Systems today announced it has closed Series B Funding with investments from Intel Capital, Intel's global investment organization, and Xilinx. Funding will be used as working capital to expand Oasys' research and development team, as well as for further expansion of its worldwide support structure.

Chip Synthesis is a fundamental shift in how synthesis is applied to the design and implementation of ICs. Traditional block-level synthesis tools do a poor job of handling chip-level issues. According to Oasys, its RealTime Designer is the first design tool for physical register transfer level (RTL) synthesis of 100-million gate designs and produces better results in a fraction of the time needed by traditional logic synthesis products. It features a unique RTL placement approach that eliminates un-ending design closure iterations between synthesis and layout.

"Xilinx has licensed Oasys technology and achieved excellent results across a wide range of designs," says Salil Raje, Vice President of Software and IP Product Development at Xilinx. "We have a long-standing and productive working relationship with the Oasys team and we are pleased to extend our support through this investment."

"Oasys' technology has the potential to positively impact the design flow for VLSI chip implementation," adds Shishpal Rawat, Director, Business Enabling Programs at Design Technology Solutions Group, Intel. "This is a new way of thinking for next-generation chip design implementation. We are pleased to invest in Oasys."

"With tape-outs at 45- and 28-nanometer process nodes, Realtime Designer is the proven synthesis solution offering substantial run-time and capacity advantages for some of the world's most complex designs," remarked Paul van Besouw, Oasys' President and CEO. "Intel Capital and Xilinx have given us strategic support, and their investment will enable us to scale commercially and to continue to advance our technology."