April 11, 2012 -- Arteris SA today announced that MtekVision has selected Arteris FlexLLI MIPI Low-Latency Interface (MIPI LLI) inter-chip link IP for multiple systems-on-chip (SOCs).

As previously announced by the MIPI Alliance on February 29, 2012, MIPI LLI is a point-to-point interconnect between two chips, with round-trip latencies low enough for both chips to share a single DRAM memory. LLI uses the MIPI M-PHY as the physical interface.

"MtekVision licensed Arteris FlexLLI because it is the only silicon-proven LLI solution, and is the fastest and safest way for us to implement MIPI LLI within our SOCs," said Harry-Hanchul Jun, Vice President at MtekVision. "Unlike the configurable FlexLLI product, the MIPI LLI specification does not encompass significant items like QoS, frequency, power and clock management, SOC interconnect integration, performance simulation and automated verification. We wanted our LLI IP to adapt to our SOC interconnect, and not the other way around. Arteris FlexLLI was the obvious choice."

Arteris FlexLLI is the only silicon-proven MIPI LLI implementation, having been implemented in the industry's first systems on chip that have LLI, including the OMAP5430 from Texas Instruments. This configurable IP connects easily with SOC interconnects using AMBA AXI, OCP and proprietary protocols, as well as Arteris FlexNoC network-on-chip interconnect IP. FlexLLI also effortlessly interfaces with commercial MIPI M-PHY IP, such as the Synopsys M-PHY, as well as internally-developed M-PHYs.

For those desiring a complete LLI digital controller and M-PHY solution, Arteris and Synopsys also offer a joint solution consisting of Arteris' FlexLLI MIPI LLI digital controller IP and Synopsys' DesignWare MIPI M-PHY IP.