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 Category: News: Latest News: Tuesday, May 21, 2013
StarChip Develops High-Performance 32-bit RISC Secure Core Based on Cortus APS3s CPU  
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April 16, 2012 -- StarChip SAS has announced the development of the ARX (Fortress in Latin). The ARX CPU is a high-performance 32-bit RISC Secure Core based on Cortus' APS3s CPU. To develop its Secure Core, StarChip selected the APS3s from Cortus SA. The APS3s is a full 32-bit general-purpose CPU specifically designed to meet the requirements of embedded systems.

In addition to these state-of-the-art technical features StarChip and Cortus have signed an agreement allowing StarChip to augment the design of the APS3s to implement embedded security mechanisms. This is the starting point for StarChip to implement its GAIA strategy; a new vision of self-healing security architecture on silicon. As a result, the StarChip Secure Core will embed all the necessary technology to counter both side-channel attacks and fault-injection attacks making it ideal for applications requiring the highest levels of security.

"We have verified the quality and the efficiency of the Cortus APS3s core from our experience in the SIM controller market," said Yves Fusella, CTO of StarChip. "Having an agreement between StarChip and Cortus to modify the APS3s was also a key element in our decision of choosing the APS3 as a starting point for the ARX core. It allows the StarChip team to use the best design practices and to implement state-of-the-art and innovative security mechanisms while optimizing the overall gate count of the CPU."



Go to the StarChip SAS website to find additional information.

E-mail StarChip SAS for more information.

Read more about
StarChip SAS
and
Cortus SA
on SOCcentral.com


Keywords: ASICs, ASIC design, IP, intellectual property, cores, RISC microprocessors, MPUs, StarChip, Cortus
601/38257 4/16/2012 380 59


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