April 16, 2012 -- Mentor Graphics Corp. today announced the 10.1 release of the Questa functional verification platform, a tightly integrated solution for the functional verification of complex system-on-chip (SOC) and FPGA designs. This new release extends Mentor's technology position in verification productivity with increased simulation and verification performance, enhanced support of the Universal Verification Methodology (UVM), accelerated coverage closure, and low-power verification with comprehensive Unified Power Format (UPF) support.

"The Questa functional-verification platform contains an integrated set of technologies that address the major verification challenges faced by today's complex SOC, ASIC, and FPGA designs," said John Lenyo, Vice President and General Manager of the Design Verification Technology division of Mentor Graphics. "Design teams are looking for solutions that increase total verification throughput, improve verification quality, speed adoption of new methodologies and effectively analyze verification results. This release of the Questa platform, combined with our comprehensive Verification Academy website, brings these powerful verification solutions and 'know-how' to verification teams around the globe.”

Simulation and verification performance

The need for additional performance is at the heart of every functional-verification process. The Questa 10.1 release introduces new Questa multi-core simulation technology. Questa Multi-Core is targeted for large designs that can take advantage of modern compute systems by partitioning the design to run on multiple CPUs or computers in parallel, while maintaining a single database for debug and coverage closure. Questa Multi-Core is especially applicable to large designs with long simulation times where users have experienced from 2X to 5X run-time improvement depending on the number of cores used. In addition, the Questa 10.1 compiler and simulation engine now makes it easier to create a common testbench for use across Questa simulation and Veloce emulation platforms creating a fast path to performance acceleration.

Leading support for UVM

Mentor continues its industry-leading role of promoting UVM adoption by making it easier for verification teams to reach their unique UVM deployment goals. The Questa 10.1 platform is the first verification platform with a UVM-aware debug solution that gives engineers essential information about the operation of their dynamic, class-based testbenches in the familiar context of source code and waveform viewing that RTL designers have used for years. With additional UVM-specific views, Questa 10.1 shows the component hierarchy, class-definition tree, and other UVM settings specific to a testbench to make it easier to understand the operation of the verification environment. Together with UVM Express, UVM Connect, and UVM Questa Verification IP, the Questa 10.1 platform provides an environment where UVM users of all ability levels can achieve the productivity required to satisfy the demands of today's designs.

Unique coverage closure solutions

Managing the verification process and achieving coverage closure rank at the top of today's verification challenges, and Mentor has industry-leading solutions that address both.

The Questa Verification Manager is a complete suite of tools that helps manage verification processes, tools and data. At its heart is an updated Unified Coverage DataBase (UCDB), designed specifically to reduce verification-file-storage needs and improve analysis and query times. Mentor has contributed the UCDB to the Unified Coverage Interoperability Standard (UCIS) driven by the Accellera Systems Initiative. For process and tool management, Questa 10.1 now includes a new Run Manager control panel that makes it easier to control, configure, analyze and automate regression environments. Using Questa Run Manager, users have been able to reduce their regression run times from days to hours.

To accelerate coverage closure, Questa inFact's intelligent testbench automation generates high-quality, non-redundant stimulus that achieves coverage closure more than 10X faster than any alternative. Now with Questa 10.1, users can automatically import their existing SystemVerilog constraints and covergroups, accelerating coverage closure with minimal time and effort. Furthermore, Questa 10.1 now automatically generates SystemVerilog covergroups, simplifying the creation and understanding of coverage models.

Low-power verification

New in Questa 10.1 is support for UPF 2.0, as well as multiple new static and dynamic power checks used for both register transfer level (RTL) and gate level power verification. UPF 2.0 enables superior support for IP blocks and hard macros, as well as enabling hierarchical composition, which is required to support a power verification methodology that spans block, sub-system and system level. Mentor is taking a leading role in driving the standardization of UPF 2.0 as well as delivering market leading support of this standard.