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IRoC Introduces TFIT 2 to Allow IC Designers to Analyze and Prevent Soft Errors at Lower Geometries  
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April 17, 2012 -- IRoC Technologies has introduced TFIT 2 with a new soft error rate (SER) response model developed in conjunction with TSMC targeting 28HP process node. TSMC has collaborated with IRoC to improve SER for test and simulation.

TFIT focuses at the cell level on the impact of soft error effects on the reliability and quality of ICs. TFIT 2 lets design engineers be proactive in assessing soft error issues and in optimizing their cell design for improved resilience especially at 65nm and below.

TFIT 2 predicts the SER FIT of any CMOS digital cell. The company's algorithms capture the complexity of cosmic ray interactions with silicon very quickly and accurately, using the cell Spice netlist and layout as design input, and the transistor model and process response model provided by foundries as technology input. TFIT 2 complements IRoC's circuit-level SER assessment tool (SOCFIT) and is used to build a database of FIT rates for each individual cell used in a circuit.

According to Shi-Jie Wen, distinguished engineer at Cisco Systems, "We benchmarked TFIT with results of tests on silicon for several designs and other tools. The correlation between the simulation results and test is impressive for the TSMC 40-nm process node. Cisco is committed to continue our correlation work with TFIT on the other silicon technology nodes. TFIT is one of the best commercially available simulation tools for soft error simulation."

TFIT 2 uses TSMC process-technology characterization for soft errors. As a result, designers can acquire accurate process SER response models in TSMC advanced technology nodes.

"TSMC chose IRoC for SER test and simulation to provide customer needs from cell/lib SER assessment, to IC SER simulation and design optimization," said Ken Chen, Senior Director, TSMC Business Development. "IRoC accurately correlates with TSMC process technology, leading to unique 40-nm and 28-nm SER solutions and services for TSMC customers."

"Our collaboration with TSMC to characterize its advanced technology process nodes with regard to ionizing particle strikes has helped make TFIT results accurate within 10% to 15% of test results and very fast,” said Olivier Lauzeral, General Manager for IROC Technologies Corp. "Our experience with soft error testing, technology trends and design behavior has allowed us to constantly correlate and fine tune TFIT to make it even more accurate."

Availability

TSMC 40G and 28HP SER process models are available immediately from TSMC. Additional models for other process nodes are under development.



Go to the iRoC Technologies website to find additional information.

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iRoC Technologies
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Keywords: ASICs, ASIC design, custom IC design, EDA, EDA tools, electronic design automation, soft errors, IRoC Technologies, TFIT
601/38273 4/17/2012 281 51


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