Page loading . . .

  
 Category: News: Latest News: Monday, May 20, 2013
Milestones to Building a Successful Technology Software Company   Featured
 Printer friendly
 E-Mail Item URL

April 23, 2012 -- You are invited to join the EDA Consortium (EDAC) on May 31, 2012 for the first in a series of conversations exploring concepts and best practices for emerging companies. The first conversation will outline the critical milestones which must be conquered to take a start-up from early stages to a strong, growing, sustainable business.

The three participants in this conversation have had serial success with navigating companies through concept to successful liquidity events. The content is geared to founders and executives of software, systems, and semiconductor companies, as well as others interested in getting a birds-eye view of what companies face as they various stages of success. The participants in this conversation will be: Jim Hogan, Private Investor, Dean Drako Dean Drako, President and CEO, IC Manage; and Ravi Subramanian, President and CEO, Berkeley Design Automation.

The conversation will be held at the Silicon Valley Bank, 3005 Tasman Drive, Santa Clara, Calif. and opens with a reception at 6:00 p.m. The Emerging Companies Conversation begins at 7:00 p.m., followd by a Q&A at 8:00 p.m.

This meeting is open to non-EDAC members and there is no charge. Seating is limited, so you need to register early!



Go to the EDA Consortium (EDAC) website for details.

E-mail EDA Consortium (EDAC) for more information.

Read more about
EDA Consortium (EDAC)
on SOCcentral.com


Keywords: ASICs, ASIC design, FPGAs, field programmable gate arrays, FPGA design, EDA, EDA tools, electronic design automation, IP, intellectual property, cores, EDA Consortium (EDAC)
601/38290 4/24/2012 478 66


Designer's Mall
0.40625



 Search for:
            Site       Current Category  
   Search Options

Subscribe to SOCcentral's
SOC Explorer
Newsletter
and receive news, article, whitepaper, and product updates bi-weekly.

Exec Viewpoint

Maximizing the Value of Your Internal IP


Warren Savage
CEO, IPextreme

Exec Viewpoint

Yes, Virginia,
There Is a
Stitch-and-Ship


Dave Johnson
VP of Sales
Breker Verification

Odd Parity

Lets' Go On
with the Show!


Mike Donlin
The Write Solution

Odd Parity Archive

Barbara's Bytes

So, Just What
Is ESL


Barbara Tuck
Senior Editor,
SOCcentral

SOCcentral Job Search

SOC Design
ASIC Design
ASIC Verification
FPGA Design
CPLD Design
PCB Design
DSP Design
RTOS Development
Digital Design

Analog Design
Mixed-Signal Design
DFT
DFM
IC Packaging
VHDL
Verilog
SystemC
SystemVerilog

Special Topics/Feature Articles
3D Integrated Circuits
Analog & Mixed-Signal Design
Design for Manufacturing
Design for Test
DSP in ASICs & FPGAs
ESL Design
Floorplanning & Layout
Formal Verification/OVM/UVM/VMM
Logic & Physical Synthesis
Low-Power Design
MEMS
On-Chip Interconnect
Selecting & Integrating IP
Signal Integrity
SystemC
SystemVerilog
Timing Analysis & Closure
Transaction Level Modeling (TLM)
Verilog
VHDL
 
Design Center
Whitepapers & App Notes
Live and Archived Webcasts
Newsletters


About SOCcentral.com

Sponsorship/Advertising Information

The Home Port  EDA/EDA Tools  FPGAs/PLDs/CPLDs  Intellectual Property  Electronic System Level Design  Special Topics/Feature Articles  Vendor & Organization Directory
News  Major RSS Feeds  Articles Online  Tutorials, White Papers, etc.  Webcasts  Online Resources  Software   Tech Books   Conferences & Seminars  About SOCcentral.com
Copyright 2003-2013  Tech Pro Communications   1209 Colts Circle    Lawrenceville, NJ 08648    Phone: 609-477-6308
183.191  0.453125