April 25, 2012 -- Synopsys, Inc. today announced the release of a new Deep Trace Debug feature for users of its systems. With HAPS Deep Trace Debug, prototypers can take advantage of approximately 100 times more signal-storage capacity than the traditional memory storage employed by on-chip FPGA logic debuggers.The new Deep Trace Debug feature enhances both capacity and fault-isolation capabilities while freeing up the on-chip FPGA memory required for validating complex system-on-chip (SOC) designs.

"The Qualcomm Atheros' Wi-Fi/ Bluetooth combo products use leading-edge Wi-Fi standards to achieve Gigabit-per-second throughput, requiring advanced hardware-software validation techniques like those available in Synopsys' HAPS systems," said Manoj Unnikrishnan, Director of Engineering at Qualcomm Atheros. "Our traditional approach required multiple runs with a lot of trial and error. The high-capacity sample storage available with HAPS Deep Trace Debug allows us to quickly identify bugs and speed full system validation. In addition, HAPS Deep Trace Debug will help us improve state machine coverage, prototyping coverage, and test pattern generation."

Confirming correct functionality of high-speed interface designs often requires sampling at dozens of frequencies for several milliseconds at a time. Traditionally, designers have had to make a choice between capturing long signal trace histories that consume extensive FPGA memory resources or saving FPGA memory resources but losing detailed visibility into signal trace history. By pairing the Synopsys Identify Intelligent Integrated Circuit Emulator (IICE) with a HAPS Deep Trace Debug SRAM daughter board, HAPS Deep Trace Debug allows many unique signal probes with complex triggers to be recorded and provides deeper memory to store extensive state history as the system executes. The SRAM daughter board also frees up the FPGA's on-chip RAM for prototyping an SOC design's memory blocks.

"The GSI Technology NBTSRAM designed onto the HAPS Deep Trace Debug SRAM daughter board enables designers to make the best use of HAPS' interconnect bus bandwidth when performance of the SOC prototype is a high priority," said David Chapman, Vice President of Marketing and Applications Engineering at GSI Technology. "Our SRAM devices provide both pipeline and flow-through operation to provide the SOC prototyper the flexibility to choose between fast read memory response and maximum clock frequency. The combination of the GSI NBT SRAM family and Synopsys' Deep Trace Debug feature enables engineers to use their HAPS systems for SOC memory IP hosting or as an extended debug trace buffer."

Availability

HAPS Deep Trace Debug support in Synopsys' Identify RTL debugger software and HAPS Deep Trace Debug SRAM daughter boards is available immediately.